Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1996-12-27
2001-07-17
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S227000, C438S229000, C438S592000
Reexamination Certificate
active
06261882
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates, in general, to a semiconductor device and a method for fabricating the same. Particularly, the present invention relates to a semiconductor device with a bilayer conductive wiring structure and without any contact for interconnecting different types of conductive wirings, thereby contributing to the high integration of a semiconductor device. Also, the present invention is concerned with a method for fabricating the semiconductor device such that the production yield is improved.
2. Description of the Prior Art
High integration of semiconductor devices is necessarily accompanied by complicated conducting wirings, which connect one device with another. The complicated conducting wirings generally form a multilayer structure in which many contacts are formed to interconnect the wirings on each layer with each other, deleteriously affecting the topology of the overall structure of the final semiconductor devices. Such topology gives rise to a decrease in the production yield and acts as a main impediment which inhibits the further integration of semiconductor devices.
High integration of semiconductor devices also forces the channel length of a MOSFET to be shortened. In order to minimize the channel length, p type MOSFETs take advantage of a p type impurity-doped polysilicon gate. For an n type MOSFET an n type impurity-doped polysilicon gate is utilized. In such case, additional connecting lines are prepared in order for one gate line to connect the p type polysilicon with the n type polysilicon. In addition, since the connecting lines are contacted at the boundary region between the polysilicons with different impurity types, the area for the contact must be secured on designing semiconductor devices.
Besides, the different type gate lines can be electrically connected with each other only after carrying out an implantation process of respective impurities two times and a contact process. Consequently, this prior art procedure is complicated and the semiconductor devices obtained by it are difficult to highly integrate because of the large area occupied by the contact regions.
SUMMARY OF THE INVENTION
Accordingly, it is a principal object of the present invention to provide a semiconductor device with a bilayer conductive wiring structure free of the contact for conductive wirings, thereby improving its topology, and a fabrication method therefor.
It is another object of the present invention to provide a semiconductor device with a dual polysilicon gate structure in which the P type polysilicon gate is connected with the N type polysilicon gate by a bilayer conductive wiring structure without any contact, thereby significantly contributing to high integration, and a fabrication method therefor.
It is a further object of the present invention to provide a semiconductor device with a dual polysilicon gate structure in which the P type polysilicon gate is connected with the N type polysilicon gate through selective tungsten or silicide without any contact, thereby significantly contributing to high integration, and a fabrication method therefor.
In accordance with one aspect of the present invention, there is provided a method for forming conductive wirings in a semiconductor device, comprising the steps of: forming a first conductive layer on an insulating layer; forming an etch barrier layer on the first conductive layer; selectively etching the etch barrier layer by use of a first conductive wiring mask, to form an etch barrier layer pattern; forming a second blanket conductive layer over the resulting structure; forming a photosensitive film pattern by use of a second conductive wiring mask with an arrangement to overlap with said etch barrier pattern; etching the second conductive layer by use of a second conductive wiring mask, to form a second conductive wiring; etching the first conductive layer by use of a combination of the photosensitive film pattern and the etch barrier layer pattern as an etch mask, to form a first conductive wiring; and removing the photosensitive film pattern, to obtain a bilayer conductive wiring structure in which the second conductive wiring stacks up on a part of the first conductive wiring.
In accordance with another aspect of the present invention, there is provided a method for fabricating a semiconductor device having a dual polysilicon gate structure, comprising the steps of: forming a P well and an N well in a semiconductor substrate and forming an element isolating film on a predetermined area including the boundary of the P well and the N well; forming a gate oxide film, a first conductive layer and an etch barrier layer, in sequence; etching the etch barrier layer by use of a gate electrode mask consisting of two separate regions, to form an etch barrier layer pattern consisting of two separate regions; depositing a blanket second conductive layer and etching it by use of a second conductive wiring mask, to form a second conductive layer pattern, said second conductive wiring mask being arranged so as to overlap both the two separate regions of the etch barrier layer pattern; etching the first conductive layer by use of a combination of the second conductive wiring mask and the etch barrier layer as an etch mask, to form a first conductive layer pattern; implanting P type impurities into the N well and one part of the first conductive layer pattern by use of a P type ion-implanting mask, to form a P type source/drain electrode and a P type gate electrode, said P type ion-implanting mask being arranged to mask the P well region including the other part of the first conductive layer pattern; and implanting N type impurities into the P well and the other part of the first conductive layer pattern by use of an N type ion-implanting mask, to form an N type source/drain electrode and an N type gate electrode, said N type ion-implanting mask being arranged to mask the N well region including the one part of the first conductive layer pattern.
In accordance with a further aspect of the present invention, there is provided a semiconductor device, comprising: a P well and an adjacent N well in a semiconductor substrate; an element isolating film formed on a predetermined area including the boundary between the P well and the N well; gate oxide layers formed on the P well and the N well; a dual polysilicon gate structure extending from a part of the P well through the element isolating film to a part of the N well, said dual polysilicon gate consisting of a P type gate electrode and an N type gate electrode, which are on the P well region and the N well region, respectively; and a conductive layer formed on the dual polysilicon gate structure and for interconnecting the P type gate electrode and the N type gate electrode.
REFERENCES:
patent: 4050965 (1977-09-01), Ipri et al.
patent: 4289574 (1981-09-01), Radigan et al.
patent: 4785341 (1988-11-01), Ning et al.
patent: 5013678 (1991-05-01), Winnerl et al.
patent: 5037772 (1991-08-01), McDonald
patent: 5073510 (1991-12-01), Kwon et al.
patent: 5089433 (1992-02-01), Anand et al.
patent: 5223456 (1993-06-01), Malwah
patent: 5292684 (1994-03-01), Chung et al.
patent: 5356826 (1994-10-01), Natsume
patent: 5382544 (1995-01-01), Matsumoto et al.
patent: 5753534 (1998-05-01), Kim
patent: 5956617 (1999-09-01), Kimura et al.
patent: 3544539 A1 (1986-07-01), None
patent: 0 272 433 A2 (1988-06-01), None
patent: 0 452 966 A2 (1991-10-01), None
patent: 0 463 458 A1 (1992-01-01), None
patent: 2060999 (1981-05-01), None
patent: 1595545 (1981-08-01), None
patent: 2210503 (1989-06-01), None
patent: 2253938 (1992-09-01), None
patent: 55-148441 (1980-11-01), None
patent: 60-200541 (1985-10-01), None
patent: 62-073743 (1987-04-01), None
patent: 03219667 (1991-09-01), None
Osburn, C.M., et al.: Predigt 1.6: Modelling of Metal Silicide Processes. In: J. Electrochem. Soc., Vol. 140, No. 12, Dec. 1993, S. 2660-3667.
Berkovitz Marvin C.
Hyundai Electronics Industries Co,. Ltd.
Nath Gary M.
Nath & Associates PLLC
Nguyen Tuan H.
LandOfFree
Method for fabricating a semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating a semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2563840