Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-05
2001-09-25
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S152000, C438S164000, C438S241000, C438S430000
Reexamination Certificate
active
06294424
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, and more particularly a method for fabricating a semiconductor device that is capable of increasing a capacitance and decreasing a step coverage between a cell part and a periphery part by simultaneously forming a capacitor over the cell part while an element isolating process is carried out by a trench on a periphery part.
BACKGROUND OF THE INVENTION
The recent high integration trend of semiconductor devices inevitably involves a reduction in cell dimension. However, such a reduction in cell dimension causes difficulty in forming capacitors of sufficient capacitance. This is due to the capacitance being proportional to the surface area of the capacitor.
In case of a dynamic random access memory (DRAM) device constituted by one metal oxide semiconductor (MOS) transistor and one capacitor, word lines and bit lines is perpendicularly disposed on the semiconductor substrate in the vertical and horizontal directions.
In addition, a capacitor is formed to be laid across the two gates and a contact hole is formed on the middle of the capacitor. In case of a capacitor, a polysilicon film is used as a conductive film and an oxide film, and a nitride film or an ONO (oxide-nitride-oxide) are used as an dielectric film.
On the other hand, it is important to reduce the area occupied by the capacitor and still obtain a high capacitance of the capacitor for the high integration of the DRAM device.
The capacitance C of the capacitor can be expressed by the following equation:
C
=(
Eo*Er*A
)/
T
Where, Eo represents the dielectric constant in vacuum, Er represents the dielectric constant of the dielectric film, A represents the area of the capacitor, and T represents the thickness of the dielectric film.
From the equation, the capacitance C can be increased by forming the dielectric film using a dielectric material exhibiting a high dielectric constant Er. In addition, the capacitance C can be increased by reducing the thickness of a dielectric film or increasing a surface area of the capacitor.
Among these methods, the dielectric material having a high dielectric constant, for example Ta2O5, TiO2 or SrTiO3, has been studied.
Reliability such as junction breakdown voltage of these materials and characteristic of the thin film is not certain, thereby being difficult to apply in a practical device.
In addition, the reduction of the thickness of the dielectric film is destructed during drive the device so that it gives a serious problem in the reliability of the capacitor.
Furthermore, the following methods are used to increase the surface area of the storage electrode of a capacitor.
The method in which a polysilicon film is formed to a stacked structure of multiple layers so that these are passed through and then connected to each other, and form a pin structure is used or the method of forming a storage electrode of a cylindrical type on the contact is used.
With regard to increasing the surface area of the storage electrode of a capacitor, an example of a conventional method for fabricating a semiconductor device is illustrated in FIG.
1
.
FIG. 1
is a sectional view showing a conventional method for fabricating a semiconductor device.
In accordance with this conventional method, an element isolating film (not shown) and a gate insulating film
13
are sequentially formed over a semiconductor substrate
11
, then a structure stacked a mask insulating film pattern
17
is formed over a gate electrode
15
.
Impurities of low density are implanted into the semiconductor substrate
11
under the sides of the stacked structure, thereby forming a LDD region (lightly doped drain).
Thereafter, a first insulating spacer
21
is formed over a side wall of the stacked structure and then, impurities of high density are implanted into the semiconductor substrate
11
in the sides of the first insulating spacer
21
, this process forms source/drain regions
23
so that a MOS transistor is formed.
A bit line (not shown) is formed so that it is connected to the source/drain electrode
23
and then, a planarizing film
25
is formed over the resulting structure.
Then, a photoresist film pattern (not shown) exposing the portion predetermined to be a storage electrode is formed over the planarizing film
25
.
Thereafter, the planalizing film
25
is selectively etched by the photoresist film pattern as an etching mask, thereby forming a contact hole for a storage electrode and then, the photoresist film pattern is removed.
A second insulating spacer
27
is formed on the side wall of the contact hole, thereby preventing the generation of bridges between the devices.
Then, a conductive film (not shown) for a first storage electrode is formed, thereby connecting to the source/drain electrode
23
through the contact hole, then a core insulating film (not shown) is formed over the conductive film for the first storage electrode.
The core insulating film and the conductive film for the first storage electrode are selectively etched by a storage electrode mask as an etching mask.
Thereafter, a conductive film (not shown) for a second storage electrode is formed over the resulting structure and then the conductive film is etched by a blanket etching process, thereby forming a storage electrode
29
for a cylindrical type.
The core insulating film is removed and then, a dielectric film
31
and a plate electrode
33
are sequentially formed over the resulting structure.
The storage electrode is formed into a cylindrical type of a three dimensional structure to increase the surface area of a capacitor. While the capacitor is only formed over the cell part of the semiconductor substrate but the capacitor is not formed over the periphery part of the semiconductor substrate.
However, the conventional method for fabricating a semiconductor device has various problems.
In the case of the conventional method, the capacitor having a storage electrode of a three dimensional structure of a cylindrical type is only formed over the cell part of the semiconductor substrate so that a step coverage between the cell part and the periphery part is increased.
Accordingly, in the following process for forming a metal line, a part of the photoresist film pattern is washed away on the boundary region between the cell part and periphery part, thereby generating a notching phenomenon. In addition, in serious case, a short between lines is generated, thereby reducing a operational characteristic of the semiconductor device and being difficult to achieve the planarization.
Therefore, it is problematic that a process yield and a reliability of device operation is reduced.
SUMMARY OF THE INVENTION
One of the objects of the invention is to provide a method for fabricating a semiconductor device, capable of decreasing the number of process for fabricating a semiconductor device, by simultaneously forming a capacitor over the cell part while an element isolating process is carried out by a trench on a periphery part.
Another object of the invention is to provide a method for fabricating a semiconductor device, capable of decreasing a step coverage between a cell part and a periphery part of a semiconductor substrate, thereby improving the characteristic and reliance of the semiconductor device.
In accordance with one aspect of the present invention, the method for fabricating a semiconductor device comprises the steps of forming a N well over a cell part and a P well over a periphery part of a semiconductor substrate, respectively; etching a portion will be predetermined a storage electrode and a portion will be predetermined an element isolating region in the semiconductor substrate, thereby forming trenches in the N well and P well; forming an isolating film over resulting structure, thereby filling the trenches; removing the insulating film on the N well; sequentially forming a dielectric layer and a conductive film over the resulting structure; selectively removing the dielectric layer and the conductive film on the P we
Kang Won Jun
Kim Yoon Nam
Yoon Hyun Gu
Berkowitz Marvin C.
Estrada Michelle
Fourson George
Hyundai Electronics Industries Co,. Ltd.
Nath Gary M.
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