Method for fabricating a semiconductor device

Details Method for fabricating a semiconductor device Method for fabricating a semiconductor device

2001-01-29

2001-08-07

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S286000, C438S299000, C438S423000, C438S520000, C438S981000

Reexamination Certificate

active

06271092

ABSTRACT:

This application claims the benefit of Korean Application No. 47188/2000, filed in the Republic of Korea on Aug. 16, 2000, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, in particular to a method for fabricating the semiconductor device which comprises transistors with an elevated source/drain structure and transistors with a normal source/drain structure.
2. Description of the Background Art
Many semiconductor manufacturers have made great efforts to improve a density of semiconductor devices. In recent years, in a field of the semiconductor devices, particularly to memory devices, transistors of a memory cell unit are designed to operate at about 1.8V of low voltage and transistors of an input/output circuit unit are designed to operate at 3.3V or 5V higher than a operating voltage of memory cell unit. Thus, a thickness of a gate insulation layer of transistors in a memory cell unit is different from a thickness of a gate insulation layer of transistors in an input/output circuit unit.
A method for fabricating devices having different thickness of gate insulation layers in one semiconductor substrate will now be described.
As shown in
FIG. 1A
, a thick oxide layer
101
is formed on the upper surface of a substrate
100
.
Then a photoresist layer
102
is formed on all upper surface of the thick oxide layer
101
and patterned by photo lithography process, thereby remaining photoresist layer
102
only on the thick oxide layer
101
of an input/output circuit unit “A” as shown in FIG.
1
B. Then, thick oxide layer
101
of a memory cell unit “B” is etched away using the photoresist layer
102
as a mask.
As shown in
FIG. 1C
, after removing the photoresist layer
102
, a thin oxide layer
103
is formed on the upper surface of the semiconductor substrate
100
of the memory cell unit “B”.
As shown in
FIG. 1D
, gate electrodes
104
are formed on the each upper surface of the thick oxide layer
101
and thin oxide layer
103
. Then lightly doped impurity regions
105
are formed in the semiconductor substrate
100
by implanting impurity ions at both sides of each gate electrode
104
.
As shown in
FIG. 1E
, sidewall spacers
106
are formed on both sides of each gate electrode
104
. Source/drain regions
107
are formed by implanting the impurity ions into the semiconductor substrate
100
at the both sides of the sidewall spacers
106
. After that, a silicide layer
108
is formed on the upper surface of the source/drain regions
107
.
However, the above-described conventional method for fabricating the semiconductor device has the below problems. In the transistors of the memory cell unit, many problems such as a short channel effect may occur because a length of the channel is very short, particularly a punch-through phenomenon, is serious. In addition, an increase of junction leakage current is a problem when the silicide layer is formed on the upper surface of the source/drain because a depth of the source/drain junction is decreased.
SUMMARY OF THE INVENTION
The present invention provides a method for fabricating a semiconductor device having transistors with an elevated source/drain structure for a memory cell unit and transistors with a normal source/drain structure for an input/output circuit, which is capable of improving density of the semiconductor device without deteriorating characteristics of the semiconductor device by differing thickness of a gate insulation layer of the input/output circuit unit and memory cell unit, restraining the short channel effect by forming the elevated source/drain structure on the memory cell unit, and decreasing a junction leakage current.
A method for fabricating a semiconductor device of the present invention comprises steps of forming a first oxide layer on an upper surface of the semiconductor substrate comprising the memory cell unit and input/output circuit unit, removing selectively the first oxide layer on the memory cell unit, forming a photoresist layer on an upper surface of the semiconductor substrate of the memory cell unit and an upper surface of the first oxide layer formed on the semiconductor substrate of the input/output circuit unit, forming openings on the region where gate electrodes will be formed by patterning the photoresist layer, forming oxygen containing layers by implanting the oxygen ions into the semiconductor substrate of the memory cell unit and in the first oxide layer through the openings, removing the photoresist layer, forming a trench in the semiconductor substrate of the memory cell unit by removing the oxygen containing layer, etching the first oxide layer as a certain thickness, forming gate electrodes on the upper surface of the first oxide layer of the input/output circuit unit and the trench on the memory cell unit, forming impurity regions by implanting the impurity ions into the semiconductor substrate at both sides of the gate electrodes, forming the sidewall spacers on the both sides of the gate electrode, and forming the source/drain regions by implanting the impurity ions into the semiconductor substrate by using the sidewall spacers as a mask.
The present invention further comprises forming a silicide layer on an upper surface of the source/drain regions.
The step of removing the oxygen containing layer of the present invention is performed by a wet etching process using a BOE (Buffered Oxide Etchant).
In the step of etching the first oxide layer to a certain thickness, the certain thickness is about ½ of the initial thickness of the first oxide layer.
The etching of the first oxide layer is performed by using a HF solution.


REFERENCES:
patent: 5480828 (1996-01-01), Hsu et al.
patent: 5920779 (1999-07-01), Sun et al.
patent: 6117711 (2000-09-01), Wu
patent: 6165849 (2000-12-01), An et al.

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