Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-26
2001-01-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S647000, C438S592000, C438S669000, C438S633000, C438S672000
Reexamination Certificate
active
06174777
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a reverse self aligned contact etch process.
2) Description of the Prior Art
The use of self aligned contact (SAC) processes has resulted in higher performing, lower cost, and increased density semiconductor devices. However, the etch to form the contact opening can cause damage to the spacers protecting the sidewalls of the structures adjacent to the contacts. Also, the tops of the structures adjacent to the contacts must withstand a significant overetch for the contact opening to be etched down to the substrate.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,661,054 (Kauffman et al.) shows a self aligned contact process. In order to completely remove the blanket deposited dielectric layer over the doped region, the top of the adjacent gate and silicon or nitride spacers must ondergo a substantial overetch which can cause reliability problems such as leakage.
U.S. Pat. No. 5,691,238 (Avanzino et al.) shows a reverse dual damascene process used to form an interconnect. Avanzino uses a timed etch of a metal layer to form a conductive via projecting up from a planer conductive layer. Avanzino does not address the self alignment and overetch problems solved by the present invention.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a self aligned contact plug using a reverse self aligned contact etch.
It is another object of the present invention to provide a method for forming a self aligned contact plug using a wherein adjacent spacers and structures are not subjected to a significant overetch.
It is another object of the present invention to provide a method for forming a self aligned contact plug which is not limited to advance type etcing machines.
It is yet another object of the present invention to provide a reliable and economical method for forming a self aligned contact plug.
To accomplish the above objectives, the present invention provides a method for forming a self aligned contact using a reverse self aligned contact etch process. The conductive layer for the contact is formed prior to the dielectric layer which separates two levels of a semiconductor device. Current self aligned contact processes form the dielectric first. A substrate structure is provided having conductive structures thereon. The conductive structures can be any of a number of structures including, but not limited to: floating gate transistors, capacitors, word lines, or a combination thereof The substrate structure also has doped regions thereon adjacent to one or both sides of the conductive structures. A polysilicon layer is formed over the conductive structures and the doped regions. A photoresist mask is formed over the polysilicon layer having openings over the conductive structures. The polysilicon layer is etched through the openings in the photoresist mask and stopping on the hard masks to form self aligned contacts over the doped regions. A dielectric layer is formed over the self aligned contacts and the conductive structures. The dielectric layer and the self aligned contacts are planarized.
The present invention provides considerable improvement over the prior art. The spacers on the sidewalls of the conductive structure are not damaged during etching because the conductive layer for the contact is formed first and the spacers are never exposed to an etch. Also, since the conductive layer is being etched and not the dielectric layer, the etch only need reach the top of the conductive structures, not the substrate, reducing the amount of overetch required. Also, the process of the present invention is not limited to an advanced type of etching machine needed to cover the high reflected power which occurs in prior processes due to exceeding the RF match in the normal working area.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5571733 (1996-11-01), Wu et al.
patent: 5631185 (1997-05-01), Kim et al.
patent: 5661054 (1997-08-01), Kauffman et al.
patent: 5691238 (1997-11-01), Avanzino et al.
patent: 5753555 (1998-05-01), Hada
Ackerman Stephen B.
Bowers Charles
Pham Thanhha
Saile George O.
Stoffel William J.
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