Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-01
2001-03-20
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S586000, C438S629000, C438S631000, C438S647000, C438S657000
Reexamination Certificate
active
06204134
ABSTRACT:
BACKGROUND OF INVENTION
1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a two step process for forming a doped polysilicon self aligned contact plug with low contact resistance.
2) Description of the Prior Art
The use of self aligned contact (SAC) processes has resulted in higher performing, lower cost, and increased density semiconductor devices. However, contact resistance is a key limitation of current SAC processes, particularly as processing speed in creases. High contact resistance and variability in contact resistance from contact to contact can reduce device life and cause reliability problems.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,807,779 (Liaw) shows a polysilicon self aligned contact process.
U.S. Pat. No. 5,763,303 (Liaw) shows a rapid thermal chemical vapor deposition procedure for a self aligned, polycide contact structure, wherein load and evacuation steps are performed in-situ at room temperature, followed by poly and tungsten depositions.
U.S. Pat. No. 5,631,179 (Sung et al.) and U.S. Pat. No. 5,607,879 (Wuu et al.) teach self aligned contact processes.
U.S. Pat. No. 5,607,724 (Beinglass et al.) shows a wafer chamber which can be used for high temperature chemical vapor deposition of polycrystalline silicon.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a self aligned contact plug using a two-step poly deposition.
It is another object of the present invention to provide a method for forming a self aligned contact plug with low Rc using a reduced thermal budget.
It is another object of the present invention to provide a method for forming a self aligned contact plug with improved step coverage and gap filling.
It is another object of the present invention to provide a method for forming a self aligned contact plug with reduced junction leakage
It is yet another object of the present invention to provide a method for forming a self aligned contact plug with improved Rc uniformity
To accomplish the above objectives, the present invention provides a method for forming a self aligned contact plug with low contact resistance in a semiconductor device using a two step process of (1) forming a high temperature polysilicon film and (2) forming a furnace doped polysilicon layer. The process begins by providing a substrate structure, having a first gate structure and a second gate structure thereon and having a contact area between the first gate structure and the second gate structure. An inter level dielectric layer is formed over the first gate structure and the second gate structure. The interlevel dielectric layer is patterned to form a self aligned contact opening over the contact area. Impurity ions are implanted into the substrate structure through the self aligned contact opening to form source and drain regions. In the key steps, a high temperature polysilicon film is formed over the source and drain regions, and a furnace doped polysilicon layer is formed over the high temperature polysilicon film. The furnace doped polysilicon layer and the high temperature polysilicon film are planarized to form a polysilicon self aligned contact plug.
The present invention provides considerable improvement over the prior art. Because HTF polysilicon provides a good interaction with the silicon substrate, contact resistance is reduced dramatically by the present invention down to about 3500 ohms. Uniformity of the contact resistance is improved as well, with a standard deviation of only about 49 ohms. The present invention also provides good step coverage typical of furnace dopd polysilicon resulting in low junction leakage properties.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5480814 (1996-01-01), Wuu et al.
patent: 5607724 (1997-03-01), Beingless et al.
patent: 5607879 (1997-03-01), Wuu et al.
patent: 5631179 (1997-05-01), Sung et al.
patent: 5763303 (1998-06-01), Liaw et al.
patent: 5792689 (1998-08-01), Yang et al.
patent: 5807779 (1998-09-01), Liaw
patent: 5930675 (1999-07-01), Hada
patent: 5943569 (1999-08-01), Shih et al.
George O. Saile
Quach T. N.
Stephen B. Ackerman
Taiwan Semiconductor Manufacturing Company
William J. Stoffel
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