Method for fabricating a salicide gate

Details Method for fabricating a salicide gate Method for fabricating a salicide gate

2000-05-09

2001-07-03

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S303000, C438S430000, C438S595000, C438S655000, C438S695000, C438S682000

Reexamination Certificate

active

06255177

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 89104924, filed Mar. 17, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a fabrication method for a salicide gate.
2. Description of the Related Art
There is a continuing effort in the semiconductor industry to increase the integration density on a semiconductor device, for example, by reducing the device dimension. As a result, the gate resistance is increased, leading to an increase of the gate response time. Currently, the common approach to reduce the gate response time and to increase the operational speed of a device is to form a salicide layer on the polysilicon gate. A polysilicon gate with a salicide layer formed thereon is known as a salicide gate.
FIG. 1A
to
1
C are cross-sectional views showing the processing of a salicide gate according to the prior art.
As shown in
FIG. 1A
, a gate oxide layer
110
and a polysilicon gate
120
is formed on a substrate
100
. Spacers
130
are further formed on the sidewalls of the gate oxide layer
110
and the polysilicon gate
120
. An ion implantation is then conducted to form a pair of source/drain regions
140
in the substrate
100
on both sides of the spacers
130
. After this, a metal layer
150
is deposited on the substrate
100
.
Continuing to
FIG. 1B
, a thermal process is conducted to induce a reaction between the metal layer
150
and the source/drain regions
140
and the polysilicon gate
120
, respectively, to form a salicide layer
170
on the source/drain region
140
and a salicide layer
160
on the polysilicon gate
120
. The unreacted metal layer
150
, as shown in
FIG. 1C
, is removed to complete the manufacturing of a salicide gate
180
.
This conventional approach in forming a salicide gate, however, has its disadvantages, especially for a dynamic random access memory (DRAM) device. Although the gate resistance is reduced in the conventional approach, a low resistance salicide layer is also formed on the source/drain regions. A higher leakage current is thus existed between the source/drain regions and the capacitor of the DRAM cell, which adversely affecting the data retention characteristics of the DRAM cell. The DRAM cell must therefore be refreshed frequently and the operational efficiency of the device is thereby reduced.
SUMMARY OF THE INVENTION
Based on the foregoing, the present invention provides an improved method in forming a salicide gate, wherein the salicide layer is only formed on the polysilicon gate but not on the source/drain regions to lower the leakage current between the source/drain regions and the capacitor of the DRAM cell.
In the method of the present invention for fabricating a salicide gate, a gate structure is formed on a substrate at first. The gate structure includes a polysilicon gate and a selective-deposition dummy layer formed thereon. Source/drain regions are then formed on both sides of the gate structure. A dielectric layer is then selectively formed on the substrate, wherein the dielectric layer on the source/drain regions is thicker than on the selective deposition dummy layer on the gate structure. A portion of the dielectric layer is then removed until the selective-deposition dummy layer is exposed. The selective-deposition dummy layer is subsequently removed to expose the polysilicon gate, followed by forming a salicide layer on the polysilicon gate to complete the formation of a salicide gate.
According to the present invention of forming a salicide gate, a thicker dielectric layer is formed on the source/drain regions. As a result, a substantial portion of the dielectric layer is still remained on the source/drain region when the dielectric layer on the selective-deposition dummy layer is being removed. The source/drain regions, being isolated by the dielectric layer, are therefore prevented from having a salicide layer formed thereon. The salicide layer hence can only be formed on the polysilicon gate.
Since the salicide layer is formed only on the polysilicon gate and not on the source/drain regions, lithography and etching of the silicide layer on the source/drain region can be avoided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5908313 (1999-06-01), Chau et al.
patent: 5956590 (1999-09-01), Hsieh et al.
patent: 6025241 (2000-02-01), Lin et al.

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