Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-03
2001-03-27
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S138000, C438S532000
Reexamination Certificate
active
06207508
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to a semiconductor device for a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), and more particularly to a RF (radio frequency) power MOSFET device having improved performance characteristics.
BACKGROUND OF THE INVENTION
Power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are commonly used in RF applications such as transmitters and receivers and other products such as plasma generators. For such applications, it is desirable that power MOSFET devices consistently strive to provide higher performance and higher frequency operation.
The performance of a power MOSFET device is closely related to its gate dimensions. A smaller gate has a shorter channel dimension than does a larger gate and the shorter channel dimension of a smaller gate contributes to high gain and efficiency of the device at high frequencies. Power output is directly proportional to the gate periphery. In addition to the channel dimensions of the gate, device performance of a power MOSFET at radio frequencies is also closely related to the capacitances of the device. First, the input capacitance of the MOSFET, referred to as C
iss
, composed of gate capacitances C
gs
and C
gd
, is critical to transistor performance. Input capacitance C
iss
is inversely proportional to the maximum frequency of the device, F
max
and hence F
t
. Thus, reducing C
iss
has the effect of increasing the maximum frequency at which the MOSFET can operate as well as the device gain and efficiency. It is therefore desirable to decrease C
gs
and/or C
gd
in order to reduce C
iss
. Conversely, it is undesirable to increase either C
gs
and C
gd
to the extent that C
iss
would be increased, for this would have the undesirable effect of producing a corresponding decrease in F
t
. As is well known in the art, C
gs
is the gate to source capacitance of the device and C
gd
is the gate to drain capacitance of the device.
Second, the feedback capacitance of the MOSFET, referred to as C
rss
, is the capacitance from the output to the input of the device and is therefore equal to gate to drain capacitance C
gd
only. The value of C
rss
is voltage dependent and is a critical dimension in the design of any power MOSFET application that uses negative feedback to obtain wide band performance.
Vertical, double diffused MOS (VDMOS) devices and in particular TMOS devices, are characterized as having two channel regions under the gate in order to increase the gate periphery to attain higher packaging density so that a higher power per unit area of the device may be achieved. The term “vertical” is descriptive of the fact that currents flow in the vertical direction of the transistor cell. The two channels are separated by an area of a drain under the gate that determines the value of C
gd
. C
gd
will obviously be decreased by decreasing the portion of the drain under the gate, but this will also serve to increase the drain resistance of the device, thereby degrading device performance, more specifically power and gain. Otherwise altering the drain region under the gate may have other, undesirable effects. For instance, increasing the doping of the drain region under the gate will lower the breakdown voltage of the device.
A typical structure of a prior art vertical MOSFET that utilizes polysilicon as part of the gate region is shown in FIG.
1
.
FIG. 1
is the prior art FIG. 1 of European patent application 84100812.5, bearing publication number 0119400, was published on Sep. 25, 1984, hereby incorporated by reference. An N−-type layer of low impurity concentration is epitaxially grown on low resistivity drain substrate
1
having an N+-type silicon wafer of high impurity concentration to form drain region
2
of high resistivity. Semiconductor wafer
4
is composed of drain substrate
1
together with drain region
2
. Next, insulating coating
3
for a gate is formed on a top surface of drain region
2
by thermal oxidation, followed by a polysilicon film that forms gate electrode
5
. Portions of the polysilicon film are selectively removed using photo-etching to open source windows. Using a double diffusion method, through the source windows thus formed, well region
6
that operates as a channel is formed. Advantages of applying the double diffusion method to a large number of transistor elements, known in the art, include uniformity in the characteristics of each transistor, improved production yield, and small transistor size. Next, source and well contact regions
7
,
8
which diffuse concentrically within well region
6
from the center outward are formed as shown. After completion of the double diffusion process, source electrode
10
is formed along the upper surface of the polysilicon gate electrode
5
through insulating film
9
by vacuum deposition. Finally, drain electrode
11
is formed on the bottom surface of drain substrate
1
as shown.
A problem with the prior art vertical MOSFET of
FIG. 1
has to do with the formation of the gate electrode
5
with respect to the drain region
2
and the large gate to drain capacitance C
gd
that results. Referring again to
FIG. 1
, it can be seen that these regions are separated only by the thin layer of insulating coating
3
, resulting in a large capacitance between the gate and drain regions. The European patent application 84100812.5 is most concerned with high switching speeds and the feedback function that the large C
gd
will serve from the output of a switching element to its input. The presence of this feedback function introduced by C
gd
makes it difficult to perform switching at high speeds. Therefore, European patent application 84100812.5, while not concerned with RF power MOSFET device applications, is nonetheless concerned with lowering C
gd
.
European patent application 84100812.5 addresses the large C
gd
problem by interposing a raised portion of oxide film between the drain region 2 and the polysilicon gate electrode 5. An enlarged portion of oxide film interposed between the drain and gate regions projects up from the drain region towards the gate and has the effect of increasing the distance between gate and drain and therefore decreasing C
gd
. The three embodiments in which an enlarged portion of oxide film is interposed between the drain and gate regions are illustrated in FIGS. 2(I), 3(G), and 4(H), respectively, of the 84100812.5 application.
While the enlarged portion of oxide film does operate to reduce C
gd
, the process required to form the enlarged portion of oxide film requires additional steps directed just to its formation, rendering the process more lengthy. In the first embodiment, shown in FIG. 2(I), it is necessary to form recess portions into which the enlarged portions of oxide film 23 are formed. The enlarged portions of oxide film are in addition to the film of silicon oxide film that is normally disposed between the gate and drain regions. In the second embodiment, shown in FIG. 3(G), thick oxide regions 125 are formed, a silicon nitride film and underlying thin oxide film removed, and then the silicon oxide insulating layer that normally exists between the gate and drain is formed. As in FIG. 2(I), thick oxide regions 125 have the effect of pushing up the peripheral portion of film 123 in order to maximize the distance between the gate and drain. Finally, in the third embodiment, shown in FIG. 4(H), the enlarged oxide bump 226 is formed by actually oxidizing a portion of polysilicon gate electrode 223.
In addition to requiring a complicated manufacturing process to form the enlarged oxide bumps, European patent application 84100812.5 has a most undesirable side effect. As shown in FIGS. 2(I), 3(G), and 4(H), the last step of forming the MOSFET device is to form the source electrode over the polysilicon portions of the gate; the gate electrode itself is not shown. The formation of the source electrode over the entire gate region, however, operates to dramatically increase the gate to source capacitance, C
gs
, of the device.
Such a substantial i
Chaudhari Chandra
Galanthay Theodore E.
Jorgenson Lisa K.
Larson Renee M.
STMicroelectronics Inc.
LandOfFree
Method for fabricating a radio frequency power MOSFET device... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating a radio frequency power MOSFET device..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating a radio frequency power MOSFET device... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2547032