Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-10-29
1999-09-28
Fourson, George
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438289, 438586, H01L 21336
Patent
active
059602902
ABSTRACT:
A method for fabricating a protection circuit for electrostatic-discharge (ESD) with an improved field device transistor includes connecting the source of the improved transistor to a ground voltage source, and connecting both the gate and the drain of the improved transistor to an I/O port and an internal circuit, which is to be protected from ESD problems. The method includes forming a gate region on a semiconductor substrate. A spacer is formed on one side of the gate region. An ion implantation process is performed to partially dope the gate region. A field oxide layer serving as a gate oxide layer is formed on the substrate within the gate region. After remove the spacer, a source region and a drain region are formed in the substrate by ion implantation. A dielectric layer is formed over the substrate with one source contact opening to expose the source region and one drain contact opening to expose the drain region. A metal layer is formed over the substrate but is separated into two parts. One part fills the source contact opening to form the source, and the other part fills the drain contact opening to form the drain and covers the field oxide layer to serve as the gate.
REFERENCES:
patent: 4602267 (1986-07-01), Shirato
patent: 5371395 (1994-12-01), Hawkins
patent: 5885875 (1999-03-01), Hsu
patent: 5895958 (1999-04-01), Miki
Fourson George
United Microelectronics Corp.
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