Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1997-06-13
2001-03-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S381000, C438S382000, C438S592000, C438S393000, C438S396000, C438S250000, C438S239000
Reexamination Certificate
active
06204105
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a method for fabricating a semiconductor device, in which, when a MOSFET, a capacitor, and a resistor which are elements for an analog integrated circuit (IC) are fabricated using a polycide and salicide process, electrodes of a capacitor are formed of polycide to minimize a resistance of the electrodes and to give a symmetry to the electrode, thus advancing the performance of the device.
2. Discussion of the Related Art
A conventional method for fabricating a semiconductor device will be described below with reference to the accompanying drawings.
FIGS. 1
a
to
1
d
are cross-sectional views showing process steps of a method for fabricating a semiconductor device.
Referring initially to
FIG. 1
a
, a field oxide layers
12
is formed on a predetermined area of a semiconductor device
11
to define an active region. Subsequently, a gate insulating layer
12
a
is grown on the entire surface of the semiconductor substrate
11
including the field oxide layer
12
. A polysilicon layer
13
, which is used as a lower electrode of a capacitor, is formed on the gate insulating layer
12
a
including the field oxide layer
12
and then a metal layer is formed thereon. Next, an annealing process is performed to form a polycide layer
14
at interface of the polysilicon layer and the metal layer. Subsequently, a dielectric layer
15
and a polysilicon layer
16
, which is used as an upper electrode of the capacitor, are successively formed on the polycide layer
14
.
Referring to
FIG. 1
b,
a first photo resist film
17
is formed on the polysilicon layer
16
and then patterned by an exposure and to development process. Using the photo resist pattern
17
as a mask, the polysilicon layer
16
and the dielectric layer
15
are selectively removed by an etching process to form an upper electrode
16
a
of the capacitor.
Referring to
FIG. 1
c
, the remaining photo resist film
17
is removed, and then a second photo resist film
18
is coated on the polysilicon layer including the upper electrode
16
a
and patterned by an exposure and development process so that the second photo resist film is remained enough to cover the dielectric layer
15
and the upper electrode
16
a.
Referring to
FIG. 1
d,
using the second photo resist pattern
18
as a mask, the polycide layer
14
and the polysilicon layer
13
are successively removed to form a lower electrode
13
a
. Next, a polysilicon for a resistor pattern is formed on the semiconductor substrate
11
including the upper electrode
16
a
of the capacitor and then is selectively removed to form a resistor pattern
19
made of polysilicon on a predetermined area of the field oxide layer
12
. A gate electrode
20
is formed on the semiconductor substrate
11
of the active region. Accordingly, there are formed the lower electrode made of polycide and the upper electrode made of polysilicon. And the gate electrode and the resistor pattern
19
are made of polysilicon.
The conventional method for fabricating a semiconductor device has the following problems.
First, a MOSFET, a capacitor, and a resistor, which are elements constituting an analog IC, are formed by respective processes and therefore the overall process is complex.
Second, since the material of a resistor used as a resistance and the material of electrodes of a capacitor are all made of polysilicon, the resistance of the electrode of a capacitor is increased, thereby increasing the delay of signals and power loss.
SUMMARY OF THE INVENTION
Therefore, the present invention is directed to a method for fabricating a semiconductor device that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An object of the invention is to provide a method for fabricating a semiconductor device suitable for a super high speed IC by minimizing a resistance of a capacitor by forming electrodes of a capacitor with silicide-polycide and a resistor with polysilicon.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the method for fabricating a semiconductor device includes the steps of forming a field oxide layer on a field region of a semiconductor substrate where a field region and an active region are defined, forming a polycide layer on the entire surface of the semiconductor substrate including the field oxide layer and selectively removing the polycide layer to form a gate electrode and a lower electrode of a capacitor, successively forming a dielectric layer and a polysilicon layer on the entire surface including the lower electrode of the capacitor and patterning the dielectric layer and the lower electrode to form an upper electrode pattern and a resistor pattern, and forming an insulating layer around the resistor pattern and forming a polycide layer on the upper electrode of the capacitor.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5107322 (1992-04-01), Kimura
patent: 5356826 (1994-10-01), Natsume
patent: 5391906 (1995-02-01), Natsume
patent: 5470775 (1995-11-01), Nariani
patent: 5472892 (1995-12-01), Gwen et al.
patent: 5597759 (1997-01-01), Yoshimori
patent: 5618749 (1997-04-01), Takahashi et al.
patent: 5701025 (1997-12-01), Yoshimori
patent: 5723352 (1998-03-01), Shih et al.
patent: 5924011 (1999-07-01), Huang
Gurley Lynne A.
LG Semicon Co. Ltd.
Morgan & Lewis & Bockius, LLP
Niebling John F.
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