Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-03-29
2001-05-29
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S258000, C257S316000, C257S324000
Reexamination Certificate
active
06238977
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 88103369, filed Mar. 5, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a source line so as to connect source regions of memory cells in a non-volatile memory.
2. Description of Related Art
Typically, several source regions abutting a word line of a non-volatile memory, such as a flash memory, are electrically coupled together by a source line and is usually formed by a self-aligned source (SAS) process. The SAS process includes, using formed stacked gates as a mask, removing field oxide (FOX) structures, which are originally used to isolate the source regions. The exposed portion of the substrate is implanted with ions so that the source region are electrically coupled together to form the source line.
As the device integration increases, the FOX structure is replaced by a shallow trench isolation (STI) structure. In this situation, the STI structure causes several problems on the SAS process to form a source line. Since an aspect ratio of the STI structure is large, it leaves a trench after the STI structure is removed. When a subsequent process to form a spacer for other elements, a trench spacer is also formed on each sidewall of the trench with a large thickness. A stress then occurs and particularly occurs on the corners to cause a leakage current. Moreover, if the trench depth is large, voids may easily occurs when the trench is filled with inter-layer dielectric (ILD) layer.
SUMMARY OF THE INVENTION
It is at least an objective of the present invention to provide a method for fabricating in a non-volatile memory. By forming a conductive layer on source regions and isolation structures, the source regions coupled together to form a source line without a conventional SAS process. Since the isolation structure, such as a STI structure, is not necessary to be removed, a leakage current is avoided and a poor performance of step coverage is also avoided during forming an inter-layer dielectric (ILD) layer.
In accordance with the foregoing and other objectives of the present invention, a method for fabricating in a non-volatile memory is provided. The method includes providing a substrate having a memory region. An isolation structure is first formed on the substrate. A stacked gate structure is then formed on the substrate at the memory region. A source region is formed abutting the stacked gate structure, while it is still not continuous due to a separation from the isolation structure. A drain region is also formed abutting the stacked gate structure on the opposite side but not actually related to the invention. A first spacer is formed on each sidewall of the stacked gate structure. A conductive layer is formed over the substrate and is patterned to remove a portion of the conductive layer. A remaining portion of the conductive layer covers the isolation structure and the source region so as to form a source line, which has an electrical coupling to each source region belonging to a same source line. The stacked gate structure is therefore exposed.
In the foregoing, the conductive layer includes, for example, titanium, titanium/titanium-nitride, Cobalt, tungsten, or other metallic material, and has a thickness of about 500-1000 angstroms. The conductive can be patterned by including, for example, forming a dielectric layer on the conductive layer. A portion of the dielectric layer other than the source region and the isolation structure is removed to exposed a portion of the conductive layer. Using the patterned dielectric layer as an etching mask, the exposed portion of the conductive layer is removed by, for example, wet etching. The remaining portion of the conductive forms a source line to connect several source regions.
During fabricating the memory region, a logic region on the substrate is usually simultaneously fabricated. The method of the invention is also suitable for this manner. In the above fabrication process, when the stacked gate structure is formed, an usual gate is also formed on the substrate at the logic region. Before the first spacer is formed, using the stacked gate structure as a mask, a first doping process is performed to pre-form a source region abutting the stacked gate structure. Using the usual gate structure at the logic region as a mask, a lightly doping process is performed so as to form a lightly doped drain (LDD) structure. A second spacer on each sidewall of the usual gate at the logic region is formed. Using the stacked gate structure and the usual gate with the second spacer as a mask, a second doping process is performed to formed desired source/drain regions at the memory region and the logic region. The first spacer is then formed on each sidewall of the stacked gate structure and the rest processes of the invention described above are performed to form the source line.
In the invention, the source line is formed without including a conventional SAS process. There is no need of a process to removed the isolation structure, a leakage current is avoided. A better step coverage performance is achieved when an ILD layer is formed, in which the improvement is more obvious for a STI structure.
REFERENCES:
patent: 5208472 (1993-05-01), Su et al.
patent: 5763312 (1998-06-01), Jeng et al.
patent: 5888869 (1999-03-01), Cho et al.
patent: 5888870 (1999-03-01), Gardner et al.
patent: 6017796 (2000-01-01), Chen et al.
Bowers Charles
Brewster William M.
Huang Jiawei
J.C. Patents
United Integrated Circuits Corp
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