Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-04-19
2005-04-19
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S265000, C438S275000, C438S287000, C438S786000, C438S791000, C438S954000
Reexamination Certificate
active
06881619
ABSTRACT:
A method for fabricating a non-volatile memory is provided. A stacked structure including a tunneling layer, a trapping layer, a barrier layer, and a control gate is formed on a substrate. A source region and a drain region are formed beside the stacked structure in the substrate. A silicon oxide spacer is formed on the sidewalls of the stacked structure. An ultraviolet-resistant lining layer is formed on the surfaces of the substrate and the stacked structure to prevent the ultraviolet light from penetrating into the trapping layer. A dielectric layer is formed on the ultraviolet-resistant lining layer. A contact being electrically connected to the control gate is formed in the dielectric layer. A conducting line electrically connected to the contact is formed on the dielectric layer. A lost-surface-charge lining layer is formed on the surfaces of the dielectric layer and the conducting line to reduce the antenna effect.
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Lee Ming-Tung
Lin Chao-Ching
Jiang Chyun IP Office
Macronix International Co.
Thomas Toniae M.
Wilczewski Mary
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