Method for fabricating a non-volatile memory

Details Method for fabricating a non-volatile memory Method for fabricating a non-volatile memory

2002-01-22

2004-03-16

Cuneo, Kamand (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

Reexamination Certificate

active

06706575

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a non-volatile memory (NVM).
2. Description of Related Art
The non-volatile memory is widely used in many fields since the data stored in a non-volatile memory is retained when power is being not supplied to the non-volatile memory. The family of the non-volatile memory includes the mask read-only memory (Mask ROM) and the nitride read-only memory (NROM), which two have similar structures.
Refer to FIGS.
1
A~
1
D, FIGS
1
A~
1
D illustrate a process flow of fabricating a non-volatile memory in the prior art in a cross-sectional view.
Refer to
FIG. 1A
, a substrate
100
is provided. A strip stacked structure
101
comprising a gate oxide layer
102
(or a charge trapping layer
102
), a polysilicon layer
104
and a nitride cap layer
105
is formed on the substrate
100
. A buried drain
106
is then formed in the substrate
100
beside the strip stacked structure
101
.
Refer to
FIG. 1B
, an insulating layer
108
is formed over the substrate
100
covering the strip stacked structure
101
.
Refer to
FIG. 1C
, the insulating layer
108
is etched back to expose the nitride cap layer
105
and then the nitride cap layer
105
is removed. The insulating layer
108
thus covers only the buried drain
106
.
Refer to
FIG. 1D
, a conductive layer
110
is then formed over the substrate
100
covering the polysilicon layer
104
and the insulating layer
108
. The conductive layer
110
and the polysilicon layer
104
are then patterned successively to form a plurality of word-lines perpendicular to the buried drain
106
and a plurality of gates, respectively. The gates arranged in one row electrically connect with one word-line.
In the process described above, the conductive layer
110
usually comprises tungsten silicide (WSi
x
). However, since the tungsten silicon process requires a temperature higher than 1000° C., the dopants in the buried drain
106
easily diffuse out to shorten the channel between two buried drains
106
. Therefore, the scalability of the memory device is restricted in consideration of the short channel effect (SCE). Moreover, the tungsten silicide word-lines have a higher resistance so that the performance of the memory device is hard to improve.
SUMMARY OF THE INVENTION
Accordingly, this invention provides a method for fabricating a nonvolatile memory to facilitate the scaling down of a memory device.
This invention provides a method for fabricating a non-volatile memory to enhance the performance of the memory device.
This invention provides a method for fabricating a NROM. A substrate having a strip stacked structure thereon is provided. The strip stacked structure comprises a conductive layer and a charge trapping layer, wherein the charge trapping layer can be a silicon oxide/silicon nitride/silicon oxide (ONO) stacked layer, a nitride
itride
itride (NNN) stacked layer, or a nitride
itride/oxide (NNO) stacked layer. A buried drain is then formed in the substrate beside the strip stacked structure and an insulating layer is formed on the buried drain. A polysilicon layer and a cap layer are sequentially formed over the substrate. The cap layer, the polysilicon layer and the strip stacked structure are successively patterned in a direction perpendicular to the buried drain, wherein the strip stacked structure is patterned into a plurality of gates. A liner oxide layer is formed on the exposed surfaces of the gates, the substrate, and the polysilicon layer by thermal oxidation. Thereafter, the cap layer is removed, a metal layer is formed over the substrate, and then an annealing process is conducted to cause the metal to react with the polysilicon layer to form a metal salicide (self-aligned silicide) layer. The unreacted metal layer is then removed to leave the metal salicide layer to serve as a word-line that is electrically connected with the gates.
In the method for fabricating a NROM of this invention, the metal layer may comprise titanium (Ti) or cobalt (Co). When a titanium layer is adopted, the annealing process requires a temperature from about 600° C. to about 800° C. When a cobalt layer is adopted, on the other hand, the annealing process requires a temperature from about 600° C. to about 700° C.
This invention also provides a method for fabricating a Mask ROM, which is similar to the above-mentioned method for fabricating a NROM of this invention, except that a gate dielectric layer, instead of the charge trapping layer, is formed on the substrate.
Since the temperature required in the metal salicide process in this invention is lower than that required in the tungsten silicide process in the prior art, the thermal budget is decreased and scaling down the memory device is therefore easier.
Moreover, since the resistance of the metal salicide (titanium/cobalt salicide) word-line in this invention is lower than that of the tungsten silicide word-line in the prior art, the performance of the memory device can be enhanced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6531350 (2003-03-01), Satoh et al.

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