Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-10-14
2002-08-06
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S108000, C438S611000, C438S621000, C438S622000, C438S638000, C438S670000
Reexamination Certificate
active
06429114
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a multilayer ceramic substrate for use in various electronic appliances, and the manufacturing method therefor.
BACKGROUND OF THE INVENTION
In order to meet the recent market preference for the smaller electronic appliances, dimensions of electronic components to be built in such appliances have been shrinking remarkably. The same goes with printed circuit boards and multilayer ceramic substrates constituting an electronic circuit. Helped by new technologies of forming conductive elements or via holes of a circuit in smaller dimensions, or by new technologies of stacking these in a multilayered configuration the wiring density in a circuit has been and will still be increased.
A conventional method for fabricating a multilayer ceramic substrate is described in the following with reference to FIG.
19
(
a
) through FIG.
19
(
g
). In the first place, a green sheet
51
of approximately 0.2 mm thick made mainly of alumina is provided, a via hole
52
is perforated therein at a certain specific place by punching or by means of CO
2
laser, the via hole
52
is then filled with an electroconductive paste (a tungsten paste, for example) by a screen printing process or other such technology and dried to complete a via
53
. Then, a certain desired circuit pattern comprised of a conductive pattern
54
is formed on the green sheet
51
by screen-printing an electroconductive paste. A circuit substrate
55
, which being a first layer, is thus provided.
In the same way, a second-layer circuit substrate
56
, a third-layer circuit substrate
57
, and, if needed, a fourth-layer circuit substrate
58
are provided; by pressing these circuit substrates together after aligning each other to a specified relative positioning a stacked circuit substrate
59
is obtained. And then it is burned at a high temperature 900-1600° C. to make a multilayer ceramic substrate
60
. According to the above method, the circuit density may be increased by increasing the number of layers of the circuit substrate.
However, a conventional method for manufacturing a multilayer ceramic substrate has drawbacks in the following points.
(1) As a conductive pattern
54
is formed by means of screen printing, it is quite difficult to provide a conductive pattern in the dimensions finer than the line width (W)/line space (S)=75 &mgr;m/75 &mgr;m.
(2) In forming a conductive pattern
54
by screen printing, the film thickness of which goes thinner when the pattern is made finer. For example, when W=75 &mgr;m the greatest film thickness available is approximately 5 &mgr;m. This brings about a high electrical resistance of a wiring.
(3) In case that tungsten, among others, is used for the wiring, the disadvantages become increasingly significant when a wiring pattern is made finer, because the resistance of the wiring of tungsten is higher than silver (Ag) or copper (Cu) by approximately 3 to 5 times. Therefore, in many cases such a device may be unable to function as an electrical component.
(4) As both the substrate and the wiring material are burned simultaneously in a temperature as high as 900-1600° C., the shrinkage of material after burning reaches 15-20%; this leads to a substantial dimensional dispersion among the substrates. This results in a substantial dispersion in the dimensions of the wiring portion, which in turn results in an inaccuracy of connection with the very fine bumps of an LSI. This is a cause of deteriorated yield rate after mounting.
(5) Furthermore, when forming a conductive pattern
54
by screen printing, it requires the line width to be greater than 75 &mgr;m (normally it is more than 120 &mgr;m, taking the yield rate at printing and the wiring resistance into consideration). This necessitates the wirings to be formed in multiple layers if many wiring lines are to be formed within a limited space. The formation of lines in a higher number of multiple layers, and the control of dimensional accuracy within a high precision level inevitably lead to higher substrate cost.
SUMMARY OF THE INVENTION
To address the above problems, the present invention offers a multilayer ceramic substrate that provides a high wiring desity at a low wiring resistance, as well as the fabricating method therefor.
A method for fabricating a multilayer ceramic substrate in accordance with the present invention comprises the steps of manufacturing an intaglio plate of flexible resin on which a first groove corresponding to a first conductive pattern is formed and a second groove deeper than the first groove is formed at a place corresponding to a via hole of the first conductive pattern; filling the first and second grooves with an electroconductive paste, and deaerating and drying it; repeating the cycle of refilling additional electroconductive paste to replenish a volume corresponding to a decrement caused by the drying, and deaerating and drying it for a certain specific times; gluing the intaglio plate onto a ceramic substrate by applying heat and pressure; separating the intaglio plate from the ceramic substrate to transfer a pattern of the electroconductive paste onto the ceramic substrate, and burning it so as to form a first conductive pattern; forming a first insulation layer on the first conductive pattern; and forming a second conductive pattern on the first insulation layer.
Following advantage may be obtained in accordance with a preferred embodiment of the present invention:
(1) The line width of a conductive pattern may be reduced down to 10 &mgr;m. Regarding a multilayer ceramic substrate, a conductive pattern whose film thickness is as thick as 30 &mgr;m may be realized at a line width 30 &mgr;m, for example. Thus, the wiring resistance is low and the wiring density is high.
(2) A fine via pattern may be formed simultaneously when a conductive pattern is formed. Therefore, a wiring pattern thus formed may be fine and precise with a high dimensional accuracy.
(3) When an insulating layer is polished or ground, the surface is flattened. Therefore, the interlayer connection may not be deteriorated even when multiple number of layers are stacked. Further, the flattened surface of a multilayer ceramic substrate assures good connection with an LSI chip mounted with the face down.
(4) When a conductive pattern is formed on a burned ceramic substrate, the locational accuracy of land pattern provided for the connection with an LSI may be controlled within a dispersion of several micro meters, because the already burned ceramic substrate is used. As a result, an almost 100% mounting yield may be realized even when mounting a fine LSI whose pad to pad pitch is smaller than 100 &mgr;m on the surface of a fine and precise wiring pattern with the face down.
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Hayama Masaaki
Matsunaga Hayami
Mouri Noboru
Chambliss Alonzo
Chaudhuri Olik
Matsushita Electric - Industrial Co., Ltd.
Ratner & Prestia
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