Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-29
2001-01-30
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S276000
Reexamination Certificate
active
06180463
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for fabricating a multi-level mask ROM (read only memory) and, more particularly, to a method for fabricating a mask ROM having a multi-level ROM cell.
(b) Description of the Related Art
A conventional nonvolatile semiconductor memory device having an insulated gate field effect transistor (IGFET), such as MOSFET, in each memory cell generally stores a 1-bit data, namely “1” or “0”. With the demand for increasing the storage capacity in the nonvolatile semiconductor memory device, a multi-level nonvolatile semiconductor memory device is proposed recently which includes a plurality of multi-level memory cells each storing multi-level data, such as 2-bit data.
A method for fabricating a mask ROM, a typical nonvolatile semiconductor memory device, having a multi-level (or 2-bit) memory cell is described in JP-A-7-142611, for example.
FIGS. 1A
to
1
D consecutively show the fabrication process described in the publication, wherein memory cell transistors B
1
to B
4
have different thresholds Vb
1
to Vb
4
such that Vb
1
<Vb
2
<Vb
3
<Vb
4
.
All the memory cell transistors B
1
to B
4
have a common basic structure including a gate insulating film
102
formed on a semiconductor substrate
101
, a gate electrode
103
formed thereon, and source/drain diffused regions
104
in the surface region of the semiconductor substrate
101
, with a channel area disposed therebetween below the gate electrode
103
. An interlayer dielectric film
105
overlies the entire basic structure.
In
FIG. 1A
, a first resist mask
106
having first openings
107
exposing the interlayer dielectric film
105
at the memory cell transistors B
2
and B
4
is formed on the interlayer dielectric film
105
by a photolithographic technique. A first ion-implantation using boron ions is conducted through the first openings
107
and the gate electrode
103
to form first injected regions
108
at the channel areas of the memory cell transistors B
2
and B
4
. The first ion implantation assures the threshold Vb
2
for the memory cell transistor B
2
, by employing a specified dosage with an acceleration energy of about 250 keV.
Subsequently, as shown in
FIG. 1B
, portions of the interlayer dielectric film
105
overlying the memory cell transistors B
2
and B
4
are selectively etched using the first photoresist mask
106
as an etching mask to reduce the thickness of the portions of the interlayer dielectric film
105
, followed by removal of the first photoresist mask
106
.
Thereafter, as shown in
FIG. 1C
, a second photoresist mask
106
a
is formed having openings
109
for exposing memory cell transistors B
3
and B
4
, followed by a second ion-implantation through the openings
109
and the gate electrodes
103
to form injected regions
110
in the channel areas of the memory cell transistors
13
and B
4
. In this step, the reduced thickness of the interlayer dielectric film
105
in the memory cell transistor B
4
provides a larger depth for the injected region
110
in the memory cell transistor B
4
than the channel area in the memory cell transistor B
4
. The second ion-implantation assures the threshold. Vb
3
for the memory cell transistor B
3
by employing a specified dosage of the boron ions.
Thereafter, a third ion-implantation is conducted using the is second photoresist mask
106
a
as it is to form injected regions
112
in the channel area of the memory cell transistor. B
4
. In this step, an injected region
111
is formed in the gate electrode
103
of the memory cell transistor B
3
due to a larger thickness of the interlayer dielectric film
105
than the thickness of the interlayer dielectric film
105
in the memory cell transistor M. Thus, the third ion-implantation does not affect the threshold Vb
3
of the memory cell transistor B
3
while assuring the, threshold Vb
4
of the memory cell transistor B
4
, which is determined by the second ion-implantation and the third ion-implantation.
In the conventional fabrication method for the multi-level mask ROM as described above, the ion-implantation for specifying the multi-level data in the memory cell transistors (referred to as “code ion-implantation”, hereinafter) has a disadvantage in that the injected region formed by the code ion-implantation has a significant extension in the transverse direction with respect to the direction of the ion injection, as detailed below.
FIG. 2
schematically shows an exemplified top plan view showing the openings of the mask ROM in a fabrication step thereof, wherein source/drain diffused regions N
1
, N
2
and N
3
extend perpendicularly to the extending direction of the gate electrodes G
1
, G
2
and G
3
. In this configuration, the channel area of a memory cell transistor is disposed below the gate electrode, such as G
1
, between the source/drain regions, such as N
1
and N
2
. The code ion-implantation is conducted through the openings K
1
, K
2
and K
3
formed in a photoresist mask.
In the ion-implantation, the injected ions are scattered by the surface of the interlayer dielectric film or the gate electrode, especially by the diagonal surface
113
of the interlayer dielectric film
105
, when the injected ions pass through the interlayer dielectric film or the gate electrode.
The scattering is one of the factors preventing a higher integration for the memory cell transistors of the multi-level mask ROM because the transverse extension of the injected region in a memory cell transistor affects the threshold of the adjacent memory cell transistors.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a multi-level mask ROM, which is capable of suppressing a transverse extension of injected ions during the code ion-implantation of memory cell transistors, thereby reducing variations of the thresholds of the adjacent memory cell transistors.
The present invention provides, in one aspect thereof, a method for fabricating a multi-level mask ROM including a plurality of memory cell transistors, the method comprising the steps of forming a gate insulating film, a gate electrode and source/drain diffused regions in an area for each memory cell transistor of a semiconductor substrate, forming a dielectric film covering the gate electrode and the source/drain regions, planarizing the dielectric film, forming an opening in a portion of the dielectric film overlying the gate electrode in an area for a selected memory cell transistor, and injecting impurity ions through the opening and the gate electrode into a channel area of the selected memory cell transistor to obtain a desired threshold voltage of the selected memory cell transistor.
The present invention also provides, in another aspect thereof, a method for fabricating a multi-level mask ROM including a plurality of memory cell transistors, the method comprising the steps of forming a gate insulating film, a gate electrode and source/drain diffused regions in an area for each memory cell transistor of a semiconductor substrate, forming a first dielectric film covering the gate electrode and the source/drain regions, planarizing the first dielectric film, forming an etch stop layer on the first dielectric film, forming a second dielectric film on the etch stop layer, forming an opening in a portion of the second dielectric film overlying the gate electrode in an area for a selected memory cell transistor, and injecting impurity ions through the opening, etch stop layer and the gate electrode into a channel area of the selected memory cell transistor to obtain a desired threshold voltage of the selected memory cell transistor.
In accordance with the fabrication method of the present invention, the surface of the interlayer dielectric film (first dielectric film) is subjected to planarization to form a flat surface of the interlayer dielectric film, thereby preventing scattering of the implanted ions and reducing a transverse extension of the injected region.
The above and other objects, featur
Booth Richard
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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