Method for fabricating a multi-level integrated circuit...

Details Method for fabricating a multi-level integrated circuit... Method for fabricating a multi-level integrated circuit...

2005-11-22

2005-11-22

Whitehead, Jr., Carl (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

C257S049000, C257S053000

Reexamination Certificate

active

06967349

ABSTRACT:
The present invention describes a plurality of scatterometry test structures for use in process control during fabrication of a semiconductor wafer having multilevel integrated circuit chips, many of said levels having a feature size of a critical dimension. The scatterometry test structures on the wafer are at each level, suitable to measure critical dimensions. The second level and each subsequent level of the test structures are located to fit into the same footprint area as the first level.

REFERENCES:
patent: 6556652 (2003-04-01), Mazor et al.
patent: 6657736 (2003-12-01), Finarov et al.

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