Method for fabricating a MOS transistor of an embedded memory

Details Method for fabricating a MOS transistor of an embedded memory Method for fabricating a MOS transistor of an embedded memory

2001-03-01

2002-10-22

Whitehead, Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

C438S258000, C438S275000, C438S200000, C438S201000, C438S241000

Reexamination Certificate

active

06468838

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a MOS transistor of an embedded memory.
2. Description of the Prior Art
In the present computer industry, logic devices are used for data or information processing, while memory devices are used for data storage. These two types of devices can be found in almost all computers,-however they are usually found on specific chips, reserved for either logic or memory applications. Systems in which logic and memory devices are packaged separately, data signals between the two may have to pass through several levels of packaging, which can lead to undesirable propagation delays. In addition, the manufacturing costs for fabricating wafers producing only logic chips and wafers producing only memory chips are greater than if both logic and memory applications were to be incorporated on the same chip.
So with the increasing integration and consideration of performance and cost, the semiconductor industry has been motivated to integrate both memory cell array and high-speed logic circuit elements onto one chip forming a so-called embedded memory. The effect is a reduction in the surfaces of chips as well as an increase in the speed of signal processing. Please refer to
FIG. 1
to FIG.
5
.
FIG. 1
to
FIG. 5
are cross-sectional diagrams of a prior art method for manufacturing a metal-oxide-semiconductor (MOS) transistor of an embedded memory on a semiconductor wafer
10
. As shown in
FIG. 1
, the surface of the silicon substrate
12
is divided into a memory array area
14
and a periphery circuit region
16
. The memory array area
14
contains a cell well
18
, and the periphery circuit region
14
contains at least one N-well
20
and at least one P-well
22
. Each region is separated by several shallow trench isolation structures
23
.
The prior art method first involves forming a gate oxide layer
21
, a polysilicon layer
24
, a polycide layer
26
and cap layer
28
composed of silicon nitride, respectively, on the surface of the semiconductor wafer
10
. Then, as shown in
FIG. 2
, a photoresist layer
30
is formed above the cap layer
28
followed by the use of a lithographic process to simultaneously define gate patterns of both the memory array area
14
and the periphery circuit region
16
in the photoresist layer
30
. Thereafter, the patterned photoresist layer
30
is used as a mask layer to perform an etching process for removing the cap layer
28
, the polycide layer
26
and the polysilicon layer
24
down to the surface of the gate oxide layer
21
so as to simultaneously form a plurality of gates
32
above the cell well
18
of the memory array area
14
and a plurality of gates
34
above the N-well
20
and P-well
22
of the periphery circuit region
16
.
As shown in
FIG. 3
, the photoresist layer
30
above the cap layer
28
is completely removed, followed by performing an ion implantation process to form a doped region (not shown) on the surface of the silicon substrate
12
adjacent to the gates
32
,
34
. Thereafter, a rapid thermal process (RTP) is performed to drive dopants in the doped region into the silicon substrate
12
so as to form lightly doped drain (LDD)
36
of each MOS transistor.
As shown in
FIG. 4
, a silicon nitride layer (not shown) is deposited on the semiconductor wafer
10
followed by performing an an-isotropic etching process to etch back portions of the silicon nitride layer to form a spacer
38
around each gate
32
,
34
of the memory array area
14
and the periphery circuit region
16
, respectively. Then, an ion implantation process is performed to form a source and drain of each MOS transistor in the periphery circuit region
16
. A photoresist layer is first formed to cover the memory array area
14
and gates
32
,
34
of the N-well
20
. Then, N-type dopants are used to implant the surface of the P-well
22
so as to form a doped region
42
, followed by removal of the photoresist layer. Next, another photoresist layer is formed to completely cover the memory array area
14
and the gate
34
of the P-well
22
. Then, P-type dopants are used to implant the N-well
20
of the periphery circuit region
16
so as to form a doped region
40
. Thereafter, a rapid thermal process is used to drive dopants of each doped region
40
,
42
into the silicon substrate
12
so as to form the source and the drain of each MOS transistor in the periphery circuit region
16
.
Finally, as shown in
FIG. 5
, a salicide block (SAB) layer
44
is formed on the silicon substrate
12
of the memory array area
14
. Then, a self-aligned silicide process is performed in the periphery circuit region
16
for forming a salicide layer
46
on the surface of each source and drain so as to finish the process of manufacturing a MOS transistor of an embedded memory according to the prior art method.
To satisfy the requirements of integration, yield rate and process properties, a self-aligned contact (SAC) process is now widely used in the manufacturing process of the memory array area to increase misalignment tolerances. However, for simultaneously forming gates in both the periphery circuit region and the memory array area, with the consideration of electrical properties of the periphery circuit region, a polycide layer must be directly deposited on the polysilicon layer for reducing the resistance of the gate structure in the periphery circuit region. A self-aligned silicide operation is also used to form a salicide layer on each source and drain for reducing the contact interface resistance of the MOS transistors. Generally speaking, the polycide layer formed by deposition has a greater resistivity than that of the salicide layer. Hence, the electrical performance of the gate structure composed of both the polycide layer and a cap layer in the periphery circuit region differs to that of the gate structure composed of the salicide layer in the conventional periphery circuit region to result in the unfitness of the cell library established by logic circuits.
SUMMARY OF THE INVENTION
It is the primary object of the present invention to provide a method of manufacturing a MOS transistor of an embedded memory that retains the cap layer required in the self-aligned contact (SAC) process of the memory array area, and simultaneously removes the cap layer in the periphery circuit region so as to form a salicide layer on the top surface of the gate and reduce the gate resistance of the periphery circuit region.
The method of the present invention is to first define a memory array area and a periphery circuit region on the surface of the semiconductor wafer. Next, a first dielectric layer, an undoped polysilicon layer, a silicide layer, a doped polysilicon layer, a protection layer and a first photoresist layer are deposited, respectively, onto the wafer. Then, a lithographic and an etching process are performed to form a plurality of gate patterns in the protection layer on the memory array area as well as to remove the protection layer on the periphery circuit region to the surface of the doped polysilicon layer. Then, a lithography process is again used to form a plurality of gate patterns in the second photoresist layer formed on the periphery circuit region. Thereafter, the second photoresist layer and the protection layer on the memory array area are used as hard masks to etch the doped polysilicon layer, the silicide layer and the undoped polysilicon layer to the surface of the dielectric layer to simultaneously form the gates of the MOS transistors in the memory array area as well as the periphery circuit region.
Next, the second photoresist layer is removed and an ion implantation process is performed to form the lightly doped drains of each MOS transistor. Thereafter, a silicon nitride layer and a second dielectric layer are formed, respectively, on the surface of the semiconductor wafer. Then, a lithography and an etching process are performed to remove the second dielectric layer and portions of the silicon nitride layer on the periphe

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