Method for fabricating a MOS transistor of an embedded memory

Details Method for fabricating a MOS transistor of an embedded memory Method for fabricating a MOS transistor of an embedded memory

2001-01-19

2002-08-20

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S981000, C438S275000

Reexamination Certificate

active

06436759

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a MOS transistor of an embedded memory, and more particularly, to a method of manufacturing a MOS transistor with different deposition thicknesses of the gate conductors in a memory array area and in a periphery circuit region of an embedded memory.
2. Description of the Prior Art
With increasing integration, the present trend of manufacturing semiconductor integrated circuits has been to integrate memory cell arrays and high-speed logic circuit elements onto a single chip. An embedded memory composed of memory arrays and logic circuits significantly reduces the circuit area and increases the signal processing speed.
Please refer to
FIG. 1
to FIG.
9
.
FIG. 1
to
FIG. 9
are cross-sectional diagrams of a prior art method for manufacturing a metal-oxide-semiconductor (MOS) transistor of an embedded memory on a semiconductor wafer
10
. As shown in
FIG. 1
, the surface of a silicon substrate
16
is divided into a memory array area
12
and a periphery circuit region
14
, with each region separated by several shallow trench isolation (STI) structures
11
. The prior art method involves the formation of a dielectric layer
18
, a polysilicon layer
20
and an etching barrier layer
22
, respectively, on the surface of the semiconductor wafer
10
. Then, as shown in
FIG. 2
, a mask layer
24
is formed over the etching barrier layer
22
in the periphery region
14
, and an isotropic wet etching process is used to remove both the etching barrier layer
22
and the polysilicon layer
20
in the memory array area
12
.
As shown in
FIG. 3
, the mask layer
24
above the etching barrier layer
22
is then removed, followed by the stripping away of the dielectric layer
18
in the memory array region
12
to expose the substrate surface
16
. As shown in
FIG. 4
, a dielectric layer
26
is formed over the exposed substrate
16
, and serves as a gate oxide layer in the memory array area
12
. Thereafter, a polysilicon layer
28
, a tungsten silicide layer
30
and a silicon nitride layer
32
are formed, respectively, over the surface of the semiconductor wafer
10
.
In the next step, as shown in
FIG. 5
, a photoresist layer
34
is deposited over the silicon nitride layer
32
and a lithographic process is performed to define gate patterns in both the memory array area
12
and the periphery circuit region
14
. Using the photoresist layer
34
as a mask, the silicon nitride layer
32
, the tungsten silicide layer
30
and the polysilicon layer
28
are then etched to expose the dielectric layer
26
in the memory array area
12
as well as the etching barrier layer
22
in the periphery circuit region
14
. As shown in
FIG. 6
, the photoresist layer
34
is then removed, followed by the deposition of another photoresist layer
36
in the memory array area
12
to protect the gate
33
. The gate
33
includes the dielectric layer
26
, the polysilicon layer
28
, the tungsten silicide layer
30
and the silicon nitride layer
32
.
As shown in
FIG. 7
, the photoresist layer
36
and the silicon nitride layer
32
of the periphery circuit region
14
are used as hard masks to remove both the etching barrier layer
22
and the polysilicon layer
20
in the periphery circuit region
14
not covered by the silicon nitride layer
32
. Next, the photoresist layer
36
is used again as a hard mask to remove the silicon nitride layer
32
, the tungsten silicide layer
30
and the polysilicon layer
28
in the periphery circuit region
14
. Then, a gate
35
is formed in the periphery circuit region
14
, followed by the removal of the photoresist layer
36
.
As shown in
FIG. 8
, an ion implantation process is then performed to form lightly doped drains (LDD)
38
of a MOS transistor. Next, a silicon nitride layer
43
is deposited over the semiconductor wafer
10
. An anisotropic etching process is used to remove the silicon nitride layer
43
in the periphery circuit region
14
as well as to form spacers
44
on the walls of the gate
35
structures, whereby the remaining etching barrier layer
22
is removed after the formation of the spacers
44
. A source
40
and drain
42
of a MOS transistor is then formed in the periphery circuit region
14
. Finally, as shown in
FIG. 9
, a self-aligned silicide operation is carried out to form salicide layers
46
above each source
40
, drain
42
and gate
35
structure in the periphery circuit region
14
.
To satisfy the requirements of process integration and production yield rate, a self-aligned contact (SAC) process is now widely used during the formation of the contact plug in the memory array area
12
to increase misalignment tolerances. However, a salicide process is also needed to form the salicide layer
46
on the surfaces of the source
40
, the drain
42
and the gate
35
in the periphery circuit region
14
to reduce the contact interface resistance and improve the electrical performance of the logic circuits. As a result, problems such as a large difference in gate height between the memory array area
12
and the periphery circuit region
14
are produced.
In addition, a thicker polysilicon layer
20
is deposited on the semiconductor wafer
10
to avoid boron penetration from the boron doped in the NMOS gate. When simultaneously forming the polysilicon layer
20
in both the memory array area
12
and in the periphery circuit region
14
, a much thicker polysilicon layer is produced than one made by an ordinary memory process. Consequently, over-hanging and void bridges are easily formed between the two adjacent gates in the memory array area
12
during the deposition of an inter-layer dielectric (ILD) layer. As a result, short circuiting may occur when an electrical connection of the contact plug is formed between the two adjacent gates with the conductors filling in the voids.
In addition, the prior method of fabricating an embedded memory suffers from a serious topographical problem of the inter-layer dielectric (ILD) layer. More specifically, the prior art method encounters a problem resulting from a large difference in the height of the ILD layer between the memory array area
12
and the periphery circuit region
14
of an embedded memory.
SUMMARY OF THE INVENTION
It is a primary objective of the present invention to provide a method of manufacturing a MOS transistor with different deposition thicknesses of the gate conductors in a memory array area and in a periphery circuit region of an embedded memory.
It is another objective of the present invention to provide a method of manufacturing a MOS transistor of an embedded memory to reduce the step height difference of gates between the periphery circuit region and the memory array area so as to improve planarization of an inter-layer dielectric (ILD) layer.
It is still another objective of the present invention to provide a method of manufacturing a MOS transistor of an embedded memory to prevent the formation of void bridges between two gates when filling the ILD layer in the memory array area.
The method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of a semiconductor wafer and to sequentially deposit a gate oxide layer, a polysilicon layer and a dielectric layer.
Next, the polysilicon layer in the memory array area is implanted to form a doped polysilicon layer. Thereafter, the doped polysilicon layer in the memory array area is etched to a predetermined thickness and the dielectric layer in the memory array area is removed. A silicide layer and a protection layer are formed on the surface of the semiconductor wafer.
A photo-etching-process (PEP) is used to etch portions of the protection, silicide, undoped and doped polysilicon layers to form a plurality of gates. Finally, a lightly doped drain and a spacer of each MOS transistor, and a source and drain of each MOS transistor in the periphery circuit region are formed.
According to the present invention, the step height differen

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