Method for fabricating a metal oxide semiconductor transistor

Details Method for fabricating a metal oxide semiconductor transistor Method for fabricating a metal oxide semiconductor transistor

2001-08-03

2002-09-10

Pham, Long (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S302000, C438S305000, C438S306000, C438S307000, C438S525000, C438S230000, C438S231000, C438S232000

Reexamination Certificate

active

06448142

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a fabrication method for a metal oxide semiconductor transistor (MOS transistor).
2. Description of Related Art
The development of the Very Large Scale Integration (VLSI) is evolving along the line of a larger wafer size and a smaller line width. This trend of development enhances the function of integrated circuits and reduces the manufacturing cost. As the device dimension reduces for the metal oxide semiconductor transistor of integrated circuits, the channel length diminishes correspondingly to increase the operating speed of the transistor.
As the device dimension is being miniaturized, an overlapping of the depletion layer of the source/drain region and the channel often occurs due to a reduction of the channel length. The shorter the channel length, the overlapping ratio of the source/drain depletion region is higher. As a consequence, the actual channel length is reduced and such a phenomenon is known as the short channel effect (SCE). In order to resolve the above problem, a lightly doped drain (LDD) is formed. However, when the line width is less than 0.25 micron, the depth of LDD has to be further reduced. As a result, the resistance increases and the speed of the device decreases. In order to avoid the aforementioned drawbacks, a source/drain extension region with a higher dopant concentration is formed to replace the lightly doped region. The fabrication of a source/drain extension region is illustrated in
FIGS. 1A
to
1
B.
FIGS. 1A through 1B
are schematic, cross-sectional views, illustrating successive steps of fabricating a metal oxide semiconductor transistor according to the prior art.
Referring to
FIG. 1A
, a gate
102
is formed on a substrate
100
. An ion implantation
104
is further conducted on the substrate
100
to form a source/drain extension region
106
, wherein the implanted dosage is greater than 10
15
/cm
2
.
Referring to
FIG. 1B
, a spacer
108
is then formed on the sidewall of the gate
102
, followed by conducting a source/drain implantation process
110
to form a source/drain region
112
in the substrate
100
. Subsequent to the implantation process, the silicon wafer is subjected to a thermal process to repair the crystal structure and to drive-in the dopants. The thermal processing, however, would lead to a lateral diffusion of the source/drain extension region
106
and an increase of the junction depth, enhancing the short channel effect.
SUMMARY OF THE INVENTION
The present invention provides a fabrication method for a metal oxide semiconductor transistor, wherein the junction depth and the dopant profile of the source/drain region are controlled to mitigate the short channel effect. The fabrication of the deep sub-micron device is therefore achieved.
The present invention provides a fabrication method for a metal oxide semiconductor transistor, wherein a source/drain implantation is conducted on a substrate that already comprises a gate having a spacer on the sidewall of the gate to form a source/drain region in the substrate beside the spacer of the gate. Self-aligned silicide is further formed on the surface of the gate and source/drain region. A portion of the spacer is then removed to form a spacer with a triangular cross section. A tilt angle implantation is conducted on the substrate to form a source/drain extension region in the substrate under the spacer and the side of the gate. A thermal cycle process is conducted to adjust the junction depth and dopant profile of the source/drain extension region.
The present invention provides a spacer with a sharp corner to reduce the rat depth of the implanted ions in order to form a shallower source/drain extension region in the substrate under the spacer and the side of the gate. A thermal cycle process is further performed to provide a more accurate adjustment of the junction depth and the dopant profile of the source/drain extension region. The short channel effect due to a reduction of the device dimension is thereby prevented.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


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