Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-11-16
1999-09-07
Dutton, Brian
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438305, 438306, 438424, 438437, H01L 21336
Patent
active
059500905
ABSTRACT:
A method for fabricating a MOS transistor device is provided. The method contains sequentially forming an oxide layer, a polysilicon layer, and a cap layer over a semiconductor substrate. Patterning the oxide layer, the polysilicon layer, the cap layer, and the substrate forms a trench opening in the substrate. A shallow trench isolation (STI) structure is formed by filling the opening with insulating material. A first-stage gate structure is formed on the substrate by patterning the oxide layer, the polysilicon layer, and the cap layer. A top portion of the STI structure above the substrate surface is exposed. A light ion implantation is performed to form a lightly doped region. Several spacers are respectively formed on each sidewall of the first-stage gate structure and each exposed sidewall of the STI structure. A heavy ion implantation process is performed to form interchangeable source/drain regions at each side of the first-stage gate structure. The cap layer is removed to leave an opening. A conductive layer is formed over the substrate and is planarized so that a remaining portion of the conductive layer fills the opening to serve as a gate metal layer. The remaining portion of the conductive layer also fills a free space between the spacers above the interchangeable source/drain regions to form several contact plugs. A dielectric layer is formed over the substrate with second contact plugs, respectively electrically coupled to the gate metal layer and the first contact plugs.
REFERENCES:
patent: 5879983 (1999-03-01), Segawa et al.
Chen Coming
Chou Jih-Wen
Lin Tony
Dutton Brian
Pham Long
United Microelectronics Corp.
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