Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2008-04-11
2010-11-23
Pham, Thanhha (Department: 2894)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C257SE21632
Reexamination Certificate
active
07838366
ABSTRACT:
A method of fabricating a metal gate structure is provided. The method includes providing a semiconductor substrate with a planarized polysilicon material; patterned the planarized polysilicon material to form at least a first gate and a second gate, wherein the first gate is located on the active region and the second gate at least partially overlaps with the isolation region; forming an inter-layer dielectric material covering the gates; planarizing the inter-layer dielectric material until exposing the gates and forming an inter layer-dielectric layer; performing an etching process to remove the gates to form a first recess and a second recess within the inter-layer dielectric layer; forming a gate dielectric material on a surface of each of the recesses; forming at least a metal material within the recesses; and performing a planarization process.
REFERENCES:
patent: 2009/0181504 (2009-07-01), Lin et al.
Cheng Li-Wei
Hsu Che-Hua
Lin Chien-Ting
Hsu Winston
Margo Scott
Pham Thanhha
Teng Min-Lee
United Microelectronics Corp.
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