Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-08
2001-04-10
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S289000, C438S157000
Reexamination Certificate
active
06214675
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention is directed, in general, to a method of fabricating an integrated circuit and, more specifically, to a method for fabricating a merged integrated circuit device that has different transistor technologies integrated into the same chip that are optimized for different operating voltages.
BACKGROUND OF THE INVENTION
Integrated circuits have gained extensive use over the last two decades and have been incorporated into a substantial number of electronic devices. At the same time, however, the size of these integrated circuits have continuously shrunk in size to accommodate ever faster and smaller electronic devices. The varied application of the electronic devices into which integrated circuits have been placed has required different types of process modules. Thus, integrated circuit manufacturers responded by developing the capability to produce different types of these modules. In many cases, they devoted entire lines within a plant to the task of producing a particular process module. As customers' expectations of electronic devices have increased, manufacturers found that it was necessary to incorporate several different modules into one device, and in some cases, even into one chip.
The incorporation of these process modules, such as dense memory, FLASH devices, bipolar devices and analog components along with the core digital CMOS technologies is presently a daunting task. In the past, these enhancement modules have often incorporated processes that were significantly different than that required by the core digital process. In particular, enhancement modules typically use 3.3 volt technology while core digital circuits employ 2.5 volt technology. Also, circuits often required different combinations of these enhancement modules. This requirement has in the past meant that manufacturers have needed to develop, maintain and qualify numerous technologies to support the varied customer and product requirements.
Traditionally, the integration of various system-level components, such as precision analog functions, cache memory, and small-signal radio frequency (RF) with core logic has required the use of separate and mutually incompatible fabrication processes implemented as separate chips at the board level. Attempting to integrate RF and analog functions with digital functions on a single chip has not been possible in process technologies of 0.35 micron, or even 0.5 micron, because the processes associated with RF devices, such as bipolar or BiCMOS, have not been easily adaptable to the needs of digital components, and CMOS processes have not been capable of handling the high-frequency requirements of RF devices.
Separate chips with separate fabrication processes not only result in increased cost and time-to-market, but also place a significant burden on wafer fabrication plants to qualify and maintain multiple process technology lines—one for each of these unique components.
Another way in which manufacturers have attempted to address this problem has been to build the module around a single technology, such as a 3.3 volt technology and then to insert circuitry to accommodate a lower voltage device, such as a 2.5 volt CMOS technology. This type of design is typically built using a 0.33 micron gate with a thick gate oxide. While this type of configuration has allowed for both types of devices to operate on a single platform, the operation of the 2.5 volt device on the 3.3 volt platform has been found to have its own inherent disadvantages. For example, a transistor that is optimized for 3.3 volts but is operated at 2.5 volts will have lower drive current than a transistor that is optimized for 2.5 volts.
Accordingly, what is needed in the art is a process that economically and efficiently incorporates both 2.5 volt and 3.3 volt technologies into a single microchip.
SUMMARY OF THE INVENTION
To address the above-discussed deficiencies of the prior art, the present invention, in one embodiment, provides a process for fabricating merged integrated circuits on a semiconductor wafer substrate. The process comprises forming a gate oxide on the semiconductor wafer substrate, forming a first transistor having a first gate on the gate oxide, and forming a second transistor having a second gate on the same gate oxide. The first transistor is optimized to a first operating voltage by varying a physical property of the first gate, varying a first tub doping profile, or varying a first source/drain doping profile. The second transistor is optimized to a second operating voltage by varying a physical property of the second gate, varying a second tub doping profile, or varying a second source/drain doping profile of the second transistor. These physical characteristics may be changed in any combination or singly to achieve the determined optimization of the operating voltage of any given transistor.
Thus in a broad scope, the present invention provides merged, integrated technologies incorporating transistor optimized for different operating voltages, which allows for a wide range of device applications within a single chip. Moreover, because the gates of the transistors are formed on the same gate oxide, there are not only substantial savings in manufacturing costs, but there is also an increase in the performance of the transistor, which translates into a faster transistor.
In one embodiment, the process includes forming the first and second transistors to a same type of transistor that may be p-type or n-type transistors. In an alternative embodiment, the process further comprises forming a third transistor having a third gate on the gate oxide and optimizing the third transistor to a third operating voltage that may also be equal to either the first or second operating voltages. Optimizing the third transistor may be accomplished by varying a physical property of the third gate, varying a third tub doping profile, or varying a third source/drain doping profile, including any combination thereof.
Varying a physical property of the first gate, in alternative embodiments, may include forming the first gate length to a length different from a length of the second gate or forming the first gate length to a length substantially equal to the second gate length. In another embodiment, however, the first tub may be doped to a doping profile that is different from the second tub doping profile. Alternatively, the second tub doping profile may be substantially the same as the first tub doping profile.
In yet other embodiments, the process may vary the first source/drain doping profile to a doping profile that is substantially the same or is different from the second source/drain doping profile. In a particularly advantageous embodiment, the gate oxide may be formed to a thickness ranging from about 1 nm to about 20 nm.
In other embodiments, the process may further be varied by: forming the first gate to a length that is different from the second gate length or doping the first tub to a doping profile that is substantially the same as the second tub doping profile. The process may also include doping the first source/drain to a doping profile that is substantially the same as the second source/drain doping profile.
The process may, in alternative embodiments, include forming the first gate to a length substantially equal to the second gate length or varying the first tub doping profile so that it is different from the second tub doping profile. This process may also include forming a first source/drain doping profile that is substantially the same as the second source/drain doping profile.
In yet other embodiments, varying a physical property of the first gate may also include forming a first gate length that is substantially equal to the gate length of the second transistor. Alternatively, the first tub doping profile may be substantially the same as the second tub doping profile or the first source/drain doping profile may be different from the second source/drain doping profile.
The transistor may, in other embodiments, be optimized by for
Cochran William T.
Kizilyalli Isik C.
Thoma Morgan J.
Elms Richard
Lucent Technologies - Inc.
Pyonin Adam
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