Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-18
2002-09-03
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S225000
Reexamination Certificate
active
06444523
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90108179, filed on Apr. 4, 2001.
BACKGROUND OF THE INVENTION
1. Field of Invention
This invention relates to a fabrication method for a memory device. More particularly, the present invention relates to a fabrication method for a memory device that comprises a floating gate.
2. Description of Related Art
A memory device that comprises a floating gate, for example, a flash memory device or other type of electrically erasable programmable read-only memory device, is programmable, erasable and has the ability of retaining data when the power is interrupted. Furthermore, such a device is highly integrated and thus is commonly used in personal computers and electronic devices.
One of the methods to perform the program operation for the above memory device with a floating gate is channel hot electron injection, wherein a positive voltage, for example, 12 Volts, is applied to the control gate to open up the channel. An appropriate voltage, for example, 6 Volts, is concurrently applied to the drain region to form an electric field that extends from the source region to the drain region. As the bias between the source region and the drain region is great enough, hot electrons are generated in the channel region. Some of the hot electrons are injected through the tunnel oxide layer into the floating gate to perform the program operation.
As a device becomes integrated, the memory cells of the memory device are more closely packed together. For example, when channel hot electron injection is used to perform the program operation on the memory cell A of a one transistor cell (1T cell) technique type of memory device, a high voltage is applied to the control gate and concurrently a voltage is applied to the drain region of the memory cell A. However, the drain region of the memory cell B in the memory device, which is not undergoing a program operation, is connected to the drain region of the memory cell A through the same bit line. Being affected by the drain coupling effect, the floating gate of the memory cell B also experiences a current flow, leading to a current leakage at the memory cell B. This phenomenon is known as the drain-turn-on leakage. As the channel length of the memory device further being reduced, the drain-turn-on leakage effect would become more serious. The presence of the drain-turn-on leakage adversely affects the reliability of a device.
SUMMARY OF THE INVENTION
The present invention provides a fabrication method for a memory device with a floating gate, wherein the drain-turn-on leakage is prevented to increase the reliability of the memory device.
The invention provides a fabrication method for a memory device with a floating gate, wherein the method is applicable to the scale down memory device to increase the integration of the memory device.
The present invention provides a fabrication method for a memory device with a floating gate, wherein a substrate is provided. A channel doping step is performed on the substrate so that the actual threshold voltage of the memory device is greater than the preset threshold voltage of the memory device. Thereafter, a stack gate and source/drain regions are sequentially formed on the substrate to complete the fabrication of the memory device. The dopant concentration in the substrate is increased by the channel doping step, the actual threshold voltage thus increases correspondingly to prevent the drain-turn-on leakage.
According to a preferred embodiment of the present invention, the dopant concentration in the substrate is increase when the channel doping step is performed. The actual threshold voltage of the subsequently formed memory device is thus increased to prevent the drain-turn-on leakage.
Moreover, according to the fabrication method for a memory device with a floating gate of the present invention, the drain-turn-on leakage is also prevented when the device is scaled down or integration is increased. The method of the present invention is thus applicable for the fabrication of a scale down memory device to increase the integration of the memory device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Fan Tso-Hung
Lu Tao-Cheng
Pan Samuel
Tsai Wen-Jer
Booth Richard
J.C. Patents
Lindsay Jr. Walter L.
Macronix International Co. Ltd.
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