Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-06-27
2006-06-27
Weiss, Howard (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S242000, C438S388000
Reexamination Certificate
active
07067372
ABSTRACT:
A memory cell has a trench, in which a trench capacitor is disposed. Furthermore a vertical transistor is formed in the trench above the trench capacitor. A barrier layer is disposed for the electric connection of the conductive trench filling to a lower doping region of the vertical transistor. The barrier layer is a diffusion barrier for dopants or impurities that are contained in the conductive trench filling.
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Author not listed: “Vertical DRAM Cell Structure Using Vertical Transistor in the Trench Capacitor”, IBM Technical Disclosure Bulletin, IBM Corp., vol. 33, No. 3A, Aug. 1990, pp. 72-75.
Schrems Martin
Weis Rolf
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Weiss Howard
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