Method for fabricating a memory cell array

Details Method for fabricating a memory cell array Method for fabricating a memory cell array

2000-06-19

2003-03-11

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S279000, C438S303000, C438S558000, C438S586000, C438S587000

Reexamination Certificate

active

06531359

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for fabricating a memory cell array, in particular an EPROM or EEPROM memory cell array, having a silicon substrate, insulation zones disposed on the silicon substrate, and word lines disposed on the insulation zones. The method includes burying the insulation zones on the silicon substrate, forming the word lines on the insulation zones, covering the word lines with a hard mask and side wall oxides and CVD deposition of preferably an oxide or nitride laterally onto the hard mask and onto the side wall oxides in order to define spacers. The spacers are etched to form spacer channels in the insulation zones between adjoining word lines. An SAS (Self Aligned Source) resist mask is applied and patterned in such a way that each two adjacent coated word lines are masked in regions, including the spacer channel located between those word lines, while each two adjacent masked word lines of masked word line pairs remain unmasked in regions, including the spacer channel lying between those word lines. The SAS resist mask is exposed and those regions of the insulation zones which are not covered by the SAS resist mask are anisotropically etched, with a bottom of uncovered spacer channels being lowered down at least to a surface of the silicon substrate, and the SAS resist mask is removed in order to uncover a resultant structure.
Such a method is disclosed in Patent Abstracts of Japan Publication number: 09082924 A, corresponding to U.S. Pat. No. 5,736,442.
In the field of memory cell arrays, there is a constant requirement for reduction of the memory cell area, in order to ensure that arrays of that type have the highest possible integration level.
One known technology for reducing memory cell area is that which goes by the name of self-aligned source construction (Self Aligned Source: SAS) and is referred to below by the abbreviation SAS. That technology is explained for the case of EPROM memories, for example, in a paper entitled “Process and Device Technologies for 16 Mbit EPROMs with Large-Tilt-Angle Implanted p-Pocket Cell”, by Yoichi Ohshima et al., in International Electron Device Meeting 1990, pages 95 et. seq.
Accordingly, for the purpose of reducing memory cell area, through the use of a special photographic technique (open on the source side) the insulation, which is usually field oxide, between active zones, so-called S/D zones, and word lines is removed through the use of dry etching technology (RIE), and source zones are implanted using the same resist mask.
A further application of that technology is explained for EEPROM memories in U.S. Pat. No. 5,264,718, where special measures are taken in order to replace the otherwise customary dog bone-shaped field oxide regions by ones with rectangular contours.
In all known cases, the above-mentioned technology for reducing memory cell area is used exclusively in combination with field oxide for the insulation, since only in that way has it been possible heretofore to obtain gradual transitions in the substrate between the field oxide and previously defined diffusion zones. In that case, the doping is effected in such a way that the bare Si substrate is doped vertically through the use of conventional high-current implantation. A spacer technology is usually used in order to protect gate edges during the actual SAS etching in that process.
Lately, use has increasingly been made of STI (Shallow Trench Isolation) constructions, according to which virtually box-shaped insulation zones are buried in the Si substrate sequentially through the use of trench etching, a filling process and an etching back or polishing back process. If the STI technology is employed for the SAS technology, the vertical side walls are not doped, or are only weakly doped, at the instant of the high-current implantation, which is effected in the vertical direction. The consequence is that only very high-impedance contiguous source zones can be obtained in the fabrication of memory cell arrays through the use of that combination of the two technologies.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a memory cell array, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type and which ensures that low-impedance contiguous diffusion regions can be obtained for the memory cell arrays without complicated implantation and with simultaneous integration of an insulation oxide.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a memory cell array, in particular an EPROM or EEPROM memory cell array, which comprises burying insulation zones on a silicon substrate by applying STI (Shallow Trench Isolation) technology, forming word lines on the insulation zones, covering the word lines with a hard mask and side wall oxides, CVD depositing an oxide or a nitride laterally onto the hard mask and onto the side wall oxides to define spacers, and etching the spacers to form spacer channels in the insulation zones between adjoining word lines. The method also includes applying and patterning an SAS (Self Aligned Source) resist mask to mask each two adjacent coated word lines in regions, including the spacer channel located between the word lines, while each two adjacent masked word lines of masked word line pairs remain unmasked in regions, including the spacer channel lying between the word lines. The SAS resist mask is exposed, regions of the insulation zones not covered by the SAS resist mask are anisotropically etched and a bottom of uncovered spacer channels is lowered down at least to a surface of the silicon substrate. The SAS resist mask is removed to uncover a resultant structure, a PSG (phosphorus-doped glass) layer is deposited onto the uncovered structure, and a resultant structure is heat treated to defuse the phosphorus doping into the uncovered silicon substrate as a source doping process step.
In accordance with another mode of the invention, the removal step is followed by an aftertreatment step for the uncovered structure.
In accordance with a further mode of the invention, the etching step additionally includes overetching. In accordance with an added mode of the invention, in the etching step, the hard mask and the CVD oxide or nitride are thinned.
In accordance with an additional mode of the invention, the heat treatment step is carried out in a furnace. In accordance with yet another mode of the invention, the heat treatment step is effected through the use of RTA.
In accordance with yet a further mode of the invention, this step is followed by a step for planarizing the resultant structure. In accordance with yet an added mode of the invention, the planarization is effected through the use of CMP.
In accordance with a concomitant mode of the invention, the planarization is followed by a process for contact hole etching and filling and for metallization.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a memory cell array, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.


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