Method for fabricating a memory cell

Details Method for fabricating a memory cell Method for fabricating a memory cell

2003-02-28

2004-12-21

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S243000, C438S386000

Reexamination Certificate

active

06833302

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a method for fabricating a memory cell having a transistor and a trench capacitor that are connected to one another through a buried strap contact. The present invention relates, in particular, to a method for fabricating a DRAM memory cell having a transistor and a trench capacitor that are connected to one another through a buried strap contact.
Memory cells having trench capacitors are used in integrated circuits (ICs), such as, for example, random access memories (RAMs), dynamic RAMs (DRAMs), synchronous DRAMs (SDRAMs), static RAMs (SRAMs), and read-only memories (ROMs). The ICs use capacitors typically for the purpose of storing charge. Thus, in dynamic random access memories (DRAMs) by way of example, the charge state of the capacitor is used to represent a data bit.
Furthermore, a DRAM memory cell also includes a so-called selection transistor, which is electrically conductively connected to the capacitor. The selection transistor is typically a MOS transistor, i.e., it has a source region and a drain region that are separated from one another by a channel region. Disposed above the channel region is a gate electrode through which the current flow in the channel can be controlled. To drive the memory cell, one of the source/drain regions (S/D regions) is connected to the bit line and the gate electrode is connected to the word line of the memory. The other S/D region is connected to the capacitor.
The ongoing endeavor to minimize the memory devices fosters the design of DRAMs with a larger density and smaller characteristic size, i.e., smaller memory cell area. This could be made possible by using smaller components, that is to say, smaller capacitors too. However, reducing the size of the capacitors also lowers the storage capacitance thereof, which adversely affects the function of the memory cell: on one hand, it is no longer possible to guarantee the required reliability when reading out the stored value; and, on the other hand, the refresh frequency has to be increased in the case of DRAMs.
A solution to this problem is afforded by a trench capacitor in which the capacitor area is disposed vertically in a trench in the substrate. This configuration allows a relatively large capacitor area, i.e., a sufficiently large capacitance, in conjunction with a small surface requirement. To fabricate a trench capacitor, first, a trench is etched into a substrate. To form a first capacitor electrode, a dopant, for example, is, then, introduced into the substrate material surrounding the trench wall. The trench wall is, then, lined with a dielectric, it being possible to use ONO, for example, as the dielectric. Subsequently, the trench is filled with an electrically conductive filling material. This filling material forms the second capacitor electrode. An insulator collar is, preferably, formed in an upper region of the trench insulator, which collar prevents a leakage current toward the first electrode. Methods for fabricating trench capacitors are described, for example, in European Patent Application EP 0 491 976 B1, corresponding to U.S. Pat. No. 5,390,618 to Wild, and EP 0 971 414 A1, corresponding to U.S. Pat. No. 6,509,599 to Wurster et al.
To fabricate a memory cell, the capacitor must, finally, be connected to an S/D region of the transistor, which can be done through a strap contact, for example. The strap contact is typically formed as a buried strap contact, i.e., the contact is fabricated below the upper substrate surface, because the configuration has the advantage that it takes up less area than a strap contact located at the surface. Consequently, a buried strap contact facilitates a minimization of the memory cell.
During the fabrication of such a buried strap contact, a bridge is produced on the filling material of the second electrode in the trench, which bridge typically includes polysilicon and constitutes a part of the strap contact. A doped diffusion region is formed in that region of the monocrystalline silicon that adjoins the bridge, which diffusion region extends as far as an S/D region of the transistor. The diffusion region and the bridge together form the strap contact that produces an electrically conductive connection between the second capacitor electrode and the S/D region of the transistor. Methods for fabricating such buried strap contacts are described for example in European Patent Application EP 0 939 430 A2, corresponding to U.S. Pat. No. 6,068,928 to Schrems et al., EP 0 939 435 A1, corresponding to U.S. Pat. No. 6,329,703 to Schrems et al., and EP 0 971 414 A1.
As mentioned above, highly doped polysilicon is typically used for the electrically conductive filling material. An example of a suitable dopant is As, which is introduced into the polysilicon in a concentration of from 10
19
to 10
20
cm
−3
. As indicated by arrows in
FIG. 3
, this dopant diffuses from the filling material
3
into the polysilicon of the bridge
6
and the diffusion region
12
, i.e., the adjoining monocrystalline silicon of the substrate
1
, and, thus, produces the conductivity required for the electrical contact in the region between the capacitor and the transistor. In this case, the dopant concentration is a critical quantity: on one hand, an excessively weak doping increases the resistance of the diffusion region, which adversely affects the performance of the memory cell; and, on the other hand, an excessively high doping leads to excessive outdiffusion into the diffusion region and to a possible short circuiting of the two S/D regions of the transistor.
If the intention is to miniaturize the transistor to reduce the space requirement of the memory cells, then the channel region of the transistor is inevitably miniaturized as well. To prevent a short circuiting of the S/D regions in such a case, it would be necessary, therefore, either to reduce the dopant concentration in the filling material of the second capacitor electrode or, else, to restrict the permissible temperature range of subsequent process steps to an extent such that the outdiffusion of dopant from the filling material is sufficiently restricted.
However, as described above, reducing the dopant concentration entails the risk of an excessively high contact resistance of the capacitor. However, limiting the permissible temperature range for subsequent process steps considerably restricts the freedom in the process configuration, which is, likewise, undesirable.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a memory cell that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that improves a method for fabricating a memory cell and reduces or completely avoids the difficulties mentioned herein.
In particular, the present invention specifies a fabrication method that decouples the permissible range of process temperatures from the dopant concentration in the electrode material. Furthermore, the present invention specifies an improved fabrication method that can easily be incorporated into an existing manufacturing process. Moreover, the present invention specifies an improved fabrication method that permits a miniaturization of a memory cell transistor without adversely affecting the performance of the memory cell.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a method for fabricating a memory cell, in particular, a DRAM memory cell, which has a transistor and a trench capacitor that are connected to one another through a buried strap contact. In such a case, the method according to the invention has the following steps:
a) a trench capacitor filled with a first doped filling material is produced;
b) at least one diffusion barrier above an upper surface of the first filling material is produced;
c) a second filling material is applied above the at least one diffusion barrier to form a bridge as part of the buried strap conta

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