Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-21
2001-07-31
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S438000, C438S675000
Reexamination Certificate
active
06268246
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to electronic devices, and more particularly to an improved method for fabricating a memory cell.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices may be transistors, capacitors, resistors, and other semiconductor devices. Typically, such devices are fabricated on a substrate and interconnected to form memory arrays, logic structures, timers and other integrated circuits. One type of memory array is a dynamic random access memory (DRAM) in which memory cells retain information only temporarily and are refreshed at periodic intervals. Despite this limitation, DRAMs are widely used because they provide low cost per bit of memory, high device density, and feasibility of use.
In a DRAM, each memory cell typically includes an access transistor coupled to a storage capacitor. In order to fabricate high density DRAMs, the storage capacitors must take up less planar area in the memory cells. As storage capacitors are scaled down in dimensions, a sufficiently high storage capacity must be maintained. Efforts to maintain storage capacity have concentrated on building three-dimensional capacitor structures that increase the capacitor surface area. The increased surface area provides for increased storage capacity. Three-dimensional capacitor structures include trench capacitors and stacked capacitors.
For stacked capacitors, the storage node generally extends significantly above the surface of an underlying substrate in order to provide a large surface area and thus sufficient storage capacity. This leads to topological problems in the formation of subsequent layers in the DRAM. Such topological problems are reduced by the use of crown-type stacked capacitors that increase surface area of the storage node while minimizing height. Crown-type capacitors, however, have a high process complexity which leads to high fabrication cost and low yield.
SUMMARY OF THE INVENTION
In accordance with the present invention, an improved method for fabricating a memory cell is provided that substantially eliminates or reduces disadvantages and problems associated with previously developed systems and methods. In particular, the present invention provides a simplified method for fabricating a storage node for a memory cell that greatly reduces fabrication steps and cost.
In one embodiment of the present invention, a method for fabricating a memory cell includes forming a first access line for a storage node and forming a second access line operable to access the storage node in connection with the first access line. The first access line includes a first terminal and a second terminal. The second access line includes a conductive layer connected to the first terminal of the first access line. An opening is formed in the second access line for connection of the storage node to the second terminal of the first access line. A sidewall is formed in the opening to form a contact hole insulated from the conductor of the second access line. The storage node is formed having a self-aligned contact formed in the contact hole and connected to the second terminal of the first access line.
Technical advantages of the present invention include providing an improved method for fabricating a memory cell. In particular, the storage node for the memory cell includes a self-aligned contact that eliminates storage node contact patterning and etching processes. In addition, a first electrode for the storage node is entirely formed from a single conductive layer. As a result, conventional deposition, anneal and etch-back processes associated with electrode fabrication are eliminated. The simplified processes reduce complexity of the memory cell and thus reduce fabrication cost while increasing yield.
REFERENCES:
patent: 5706164 (1998-01-01), Jeng
patent: 5780339 (1998-07-01), Liu et al.
patent: 5789289 (1998-08-01), Jeng
patent: 6033966 (2000-03-01), Linliu
patent: 6080620 (2000-06-01), Jeng
Niuya Takayuki
Ukita Shigenari
Brady W. James
Hoel Carlton H.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Tsai Jey
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