Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-08-20
2004-11-23
Lee, Hsien Ming (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S248000, C438S249000, C438S259000, C438S261000
Reexamination Certificate
active
06821841
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a mask read-only-memory (mask ROM), and more particularly to a method for fabricating a mask ROM with diode cells.
2. Description of the Prior Art
Memory cells of a mask ROM (mask read-only-memory) are is generally made using channel transistors. Programming of the ROM is achieved by selectively implanting ions into the channels of these transistors. By implanting ions into the channel regions of specified transistors, threshold voltage of the devices changes. Hence, the “on” or “off ” state of the memory cell is coded. A mask ROM cell is formed by laying a polysilicon word line (WL) over a bit line (BL), and the memory cell channel is formed in the region underneath the word line between neighboring bit lines. Normally, each ROM cell is in a logic state of “1” or “0” depending on whether ions are implanted into the channel region or not. The advantage of being able to program the state of each ROM cell by an ion implant operation is that semi-finished ROM products can be made. Once the required program codes arrive, a mask can be made and then the final ion implant operation can be carried out, thereby shortening customers' delivery date. However, the method requires the production of one more photomask to carry out an ion implant operation. Moreover, reliability of the final ROM product is very much dependent upon the quality of the ion implant operation.
FIG. 1A
is a schematic top view of a conventional mask ROM. Referring to
FIG. 1B
, a gate oxide layer
102
is formed in a p-type substrate
100
. Gates
104
are formed over the substrate
100
as word lines. An ion implantation process is performed by using gates
104
as masks to form n-type source/drain regions
106
as bit lines. The bit lines cross the word lines perpendicularly. Channels are formed below the word lines. The state of each memory cell is determined by the channels. The method of closing the channels is to implant p-type ions into specific channels
107
to form code ion implant regions
110
.
The conventional method for fabricating the mask ROM is shown in
FIGS. 1B and 1C
. Referring to
FIG. 1B
, a p-type substrate
100
is provided. An isolation region
101
is formed in the substrate
100
. A gate oxide layer
102
and gates
104
are formed in sequence on the substrate
100
. An ion implantation process is performed by using n-type ions as dopants to form a plurality of source/drain regions
106
in the substrate
100
. Channels
107
are formed between two adjacent source/drain regions
106
.
Referring to
FIG. 1C
, a patterned photoresist layer
108
is formed over the substrate
100
to expose subsequently formed code ion implant regions. An ion implantation process is performed by using phosphrous-31 as a dopant. The implantation energy is 160 KeV and the dosage of the dopant is about 1×10
14
ions/cm
2
. After performing an annealing process at 850° C., code ion implant regions
110
are formed. The photoresist layer
108
is removed. Thus, an encoding process of the mask ROM is completed.
The conventional mask ROM device uses a channel transistor as a memory cell. The implantation of ions into the channel determines the binary data “0 ” or “1”. However, when the mask ROM device is shrunk down, the issue of the code pattern resolution is enhanced and the code ion implanted region cannot be well defined.
Accordingly, it is an intention to provide an improved method for fabricating a mask ROM, which can overcome the above drawback encountered when the mask ROM device is increasingly shrunk down.
SUMMARY OF THE INVENTION
It is one objective of the present invention to provide a method for fabricating a mask read-only-memory with diode cells, which forms a structure of a contact plug/a PN diode instead of a channel transistor as a memory cell. The process for forming the structure of the contact plug/PN diode is simple and can provide a well-defined code area even though the device dimension is shrunk down.
It is another objective of the present invention to provide a method for fabricating a mask read-only-memory with diode cells, since the area of the substrate occupied by one PN diode cell is smaller than that of a channel transistor, a high-density mask ROM device can be obtained by the present method.
It is a further objective of the present invention to provide a method for fabricating a mask read-only-memory with diode cells, which provides a simple process to form a structure of a contact plug/a PN diode instead of a channel transistor as a memory cell. Therefore, the manufacturing cost can be reduced.
In order to achieve the above objectives, the present invention provides a method for fabricating a mask read-only-memory with diode cells. A semiconductor substrate is provided and a buried diffusion layer with a first conductivity is formed in the top portion of the semiconductor substrate. A plurality of shallow trench isolation regions are formed in the semiconductor substrate, and making the buried diffusion layer to a plurality of bit lines. An interlayer dielectric layer is formed over the buried diffusion layer and the shallow trench isolation regions. A photoresist layer with a mask read-only-memory code pattern is formed on the interlayer dielectric layer. Performing an anisotropic etching process to form openings in the interlayer dielectric layer unto the exposed regions of the buried diffusion layer using the photoresist layer as an etching mask. Then, the photoresist layer is removed. Performing ion implantation to form a diffusion region, with a second conductivity opposite to the first conductivity, in each of the exposed regions of the buried diffusion layer. Thereafter, a contact plug is formed in each opening unto the diffusion region. A conductive layer is formed on the interlayer dielectric layer for serving as word lines. As a consequence, a structure of a contact plug/a diode cell is obtained, which is used as a memory cell of a mask read-only-memory (mask ROM) instead of a channel transistor. The area of the semiconductor substrate occupied by one diode cell is smaller than that of the channel transistor. Thus, a high-density mask ROM device can be obtained by the present method. Furthermore, the process for forming the structure of the contact plug/diode cell is simple and can provide a well-defined code area even through the device dimension is shrunk down. The manufacturing cost is also reduced.
REFERENCES:
patent: 6689658 (2004-02-01), Wu
Chen Huei-Huarng
Kao Hsuan-Ling
Tsai Wen-Bin
Wu Chun-Pei
Lee Hsien Ming
Macronix International Co. Ltd.
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