Method for fabricating a low trigger voltage silicon controlled

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438202, 438135, 438217, 438374, H01L 218238

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active

059665998

ABSTRACT:
A method for fabricating a semiconductor device in a substrate. Active regions are defined within the substrate using a thin oxide layer and a silicon nitride layer with portions of the silicon nitride layer being etched away to expose the thin oxide layer. Field oxide regions are formed over regions other than the defined active regions. These field oxide regions are located between the active regions. The remaining portions of the silicon nitride layer and the thin oxide layer are removed and a sacrificial oxide layer is then grown on the surfaces of the active regions. A first mask, a N-well mask, is formed for implanting N-type dopants. A buried layer implanted using P-type dopants with the first mask in place. Thereafter, the N-well regions are implanted. The first mask is removed and a second mask is formed to define regions for implanting P-well regions using P-type dopants. The P-well regions are implanted using P-type dopants.

REFERENCES:
patent: 4762802 (1988-08-01), Parrillo
patent: 5055417 (1991-10-01), Akcasu
patent: 5072273 (1991-12-01), Avery
patent: 5218249 (1993-06-01), Jordan
patent: 5274262 (1993-12-01), Avery
patent: 5292671 (1994-03-01), Odanaka
patent: 5296401 (1994-03-01), Mitsui et al.
patent: 5322804 (1994-06-01), Beason
patent: 5436176 (1995-07-01), Shimizu et al.
patent: 5455436 (1995-10-01), Cheng
patent: 5465189 (1995-11-01), Polgreen et al.
patent: 5478759 (1995-12-01), Mametani et al.
patent: 5478761 (1995-12-01), Komori et al.
patent: 5489540 (1996-02-01), Liu et al.
patent: 5573963 (1996-11-01), Sung
patent: 5693505 (1997-12-01), Kobayashi

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