Method for fabricating a LOCOS MOS device for ESD protection

Details Method for fabricating a LOCOS MOS device for ESD protection Method for fabricating a LOCOS MOS device for ESD protection

1999-02-11

2000-10-31

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438200, 438297, 438591, 438981, H01L 21336

Patent

active

061401897

ABSTRACT:
A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

REFERENCES:
patent: 5405806 (1995-04-01), Pfiester et al.
patent: 5589423 (1996-12-01), White et al.
patent: 5698457 (1997-12-01), Noguchi
patent: 5744841 (1998-04-01), Gilbert et al.

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