Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2005-02-15
2005-02-15
Zarneke, David A. (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S221000, C438S273000, C438S274000
Reexamination Certificate
active
06855581
ABSTRACT:
The present invention relates to a method of fabricating a high-voltage high-power integrated circuit device using a substrate of a SOI structure in which an insulating film and a silicon layer are sequentially stacked on a silicon substrate. The method comprising the steps of sequentially forming an oxide film and a photoresist film on the silicon layer and then performing a photolithography process using a trench mask to pattern the photoresist film; patterning the oxide film using the patterned photoresist film as a mask and then removing the photoresist film remained after the patterning; etching the silicon layer using the patterned oxide film as a mask until the insulating film is exposed to form a trench; forming a nitride film on the entire surface including the trench, performing an annealing process and depositing polysilicon on the entire surface so that the trench is buried; and sequentially removing the polysilicon and the nitride film until the silicon layer is exposed to flatten the surface, thus forming a device isolating film for electrical isolation between devices within the trench. Therefore, the present invention can effectively reduce the isolation area of the trench between the high-voltage high-power device and the logic CMOS device and can easily control the concentration of a deep well.
REFERENCES:
patent: 5416041 (1995-05-01), Schwalke
patent: 5811315 (1998-09-01), Yindeepol et al.
patent: 6130458 (2000-10-01), Takagi et al.
patent: 6461902 (2002-10-01), Xu et al.
SOI High Voltage Integrated Circuit Technology for Plasma Display Panel Drivers by M.R. Lee et al. pp. 285-288.
Application of Partially Bonded SOI Structure To An Intelligent power Device Having Vertical DMOSFET by K. Kobayashi et al., pp. 309-312.
Kim Jong Dae
Kim Sang Gi
Koo Jin Gun
Lee Dae Woo
Park Il Yong
Blakely , Sokoloff, Taylor & Zafman LLP
Electronics and Telecommunications Research Institute
Kilday Lisa
Zarneke David A.
LandOfFree
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