Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-02-11
2004-01-27
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S259000, C438S264000, C438S266000
Reexamination Certificate
active
06682977
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor fabrication method. More particularly, the present invention relates to a method for fabricating a flash memory device, which can provide a larger coupling ratio between the floating gate and the control gate and which further has a high memory cell density.
2. Description of Related Art
Currently, a flash memory with a high memory cell density has significant applications in various apparatus designs. One main advantage of the flash memory is that each memory cell can be fabricated with greatly reduced dimensions, and fabrication cost is also greatly reduced. In a conventional flash memory, memory cells are isolated by a field oxide (FOX) structure that is formed by local oxidation (LOCOS). The dimensions of the FOX structure can only be reduced within certain limits. As a result, cell density is also limited.
Another typical isolation structure is a shallow trench isolation (STI) structure. Since the STI structure can be formed in a much smaller area than the FOX structure, application of the STI structure in a flash memory can effectively minimize the cell dimension so that the cell density can be ultimately increased.
However, in this method, an overlapping area between a floating gate and a control gate of the flash memory is accordingly small. This results in a smaller coupling ratio. A smaller coupling ratio creates a need for a higher bias to be applied on the control gate when erasing the information stored in the memory cells. Moreover, the flash memory with a smaller coupling ratio requires a higher electric field to obtain a Fowler-Nordheim (F-N) tunneling effect, and results in a lower electron transmission rate between the floating gate and a source/drain region. The read/write operation therefore becomes slower. All the above problems are induced by a lower coupling ratio, which further results from dimensions being too small. The dimensions of the flash memory cell cannot be further reduced. It is a goal to fabricate a flash memory having high cell density and a high coupling rate.
Reference is made to
FIG. 1
, wherein a schematic, cross-sectional view of an “elephant-ears” floating gate used to increase the coupling ratio between the floating gate and control gate is illustrated. The “elephant-ears” floating gate is fabricated by first defining the trenches (not shown in the
FIG. 1
) for forming shallow trench isolation (STI) structures
102
in the substrate
100
by the first photolithographic and etching processes. Then, the trenches are filled with oxide and the STI structures
102
are formed in the trenches. The STI structures
102
are higher than the surface of the substrate
100
. A tunneling oxide layer
104
is formed on the substrate
100
. A polysilicon layer (not shown in the
FIG. 1
) is deposited cover the tunneling oxide layer
104
and STI structures
102
.
With further reference to
FIG. 1
, a floating gate
106
is defined by the second photolithographic and etching processes on the polysilicon layer. A dielectric layer
108
is deposited and covers the floating gate
106
and STI structure
102
. Finally, a polysilicon layer
110
is formed on the dielectric layer
108
. The polysilicon layer
110
is a control gate. Because the floating gate
106
has two “ear” structures on the STI structure
102
, it is called an “elephant-ears” structure.
Compared with traditional stacked flash memory, the “elephant-ears” stacked flash memory has a higher coupling ratio between the floating gate and control gate. However, when each memory cell is fabricated under greatly reduced dimensions, the window for alignment in forming the floating gate
106
decreases and misalignment becomes a problem.
SUMMARY OF THE INVENTION
In accordance with the above background of the invention, the conventional method of manufacturing a gate structure of a stacked flash memory has disadvantages. The misalignment in defining the floating gate will decrease the yield and since the conventional method needs two photolithographic processes to define the gate structure, fabrication costs cannot be lowered. Therefore, it is necessary to find a process for manufacturing highly integrated sub-micron semiconductors having a stacked flash memory structure that improves upon the conventional disadvantages. It is therefore an objective of the present invention to provide a method for fabricating a gate structure of a stacked flash memory, in which the coupling ratio between the floating gate and control gate is increased.
It is another object of the present invention to provide a method for fabricating a gate structure of a stacked flash memory, in which only one photolithographic and etching process is needed, thereby reducing costs of manufacture.
It is still another object of the present invention to provide a method for fabricating a gate structure of a stacked flash memory, in which the floating gate is defined by a self-aligned process. The self-aligned process avoids misalignment in forming the floating gate and the yield will increase.
In accordance with the foregoing and other objects of the present invention, a method for fabricating a gate of a flash memory is provided. A tunneling oxide layer, a first conductive layer and a dielectric layer are sequentially formed on a substrate, wherein the material for forming the first conductive layer comprises polysilicon and the material for forming the dielectric layer comprises silicon nitride. Typically, the tunneling oxide layer is formed by a thermal process. The first conductive layer and the dielectric layer are formed by a chemical vapor deposition (CVD) process.
A photo-resist layer is formed on the dielectric layer by spinning or vapor coating and the photo-resist layer is patterned by exposure and development process. Using the photo-resist layer as a mask, the dielectric layer, the first conductive layer, the tunneling oxide layer, and the substrate are etched by a time control anisotropic etching process to form a plurality of trenches in the substrate so that an active area, defined by every two trenches, is simultaneously formed.
The photo-resist layer is removed. A plurality of shallow trench isolation (STI) structures is formed in the trenches by filling the trenches with silicon oxide up to the dielectric layer. The top portion of the shallow trench isolation structures is removed by a reactive ion etching process to further expose the sidewall of the dielectric layer and a top portion of the sidewall of the first conductive layer. Part of the dielectric layer is removed by hot phosphoric acid.
Thereafter, a second conductive layer is formed on the dielectric layer and the shallow trench isolation structures, wherein the material for forming the second conductive layer comprises polysilicon. The second conductive layer is etched anisotropically to further expose the top and the face of the shallow trench isolation structures to form a floating gate and a conductive spacer is formed. The remaining dielectric layer is also removed by hot phosphoric acid. A conformal insulation layer is formed over the substrate. A third conductive layer is formed on the dielectric layer as a control gate, wherein the material for forming the second conductive layer is comprises polysilicon.
In conclusion, the invention allows the floating gate to be formed by a self-aligned method, and only one photolithographic process is needed. For this reason, the fabrication cost is also greatly reduced.
Moreover, the contact area between the floating gate and the control gate of the gate structure made by the method disclosed in this invention enjoys at least a 10% increase over that of the conventional “elephant-ears” stacked flash memory manufactured under identical conditions. Because the coupling ratio is proportional to the contact area between the floating gate and the control gate, the coupling ratio of the gate structure will also increase at least 10%.
It is to be understood that both the foregoing general description and the followin
Chen Jack
Dickinson Wright PLLC
Winbond Electronics Corporation
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