Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-08
2001-01-30
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000
Reexamination Certificate
active
06180459
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a flash memory device.
2. Description of Related Art
An erasable programmable read only memory (EPROM) device is often used in a computer or various electronic products. It has a advantage that all information including, for example, program codes or data stored in the (EPROM) device are not erased in a normal operation. The stored information can only be erased by exposing the EPROM device in an ultraviolet (UV) light for a certain time. Then, new desired information can be written in again. However, once the EPROM device is exposed to the UV light, all stored information is erased in once. Another writing-in process has to be performed from the beginning to the end, even though it may just have very few modifications only for the new updated information. In other words, it takes long for each modification or update. This causes a time consumption. Recently, the Intel company has developed a flash EPROM device, or called a flash memory, which allows the information to be erased and written-in block by block, so that the stored information can be locally modified without a need to repeat whole erasing and writing-in processes. A special memory cell used in the flash EPROM is called a EPROM with tunnel oxide cell (ETOX cell).
FIG. 1A
is a top view of a portion of a substrate, schematically illustrating a conventional layout of a flash memory.
FIG. 1B
, is a cross-sectional view of a portion of a substrate taken along a line
1
—
1
in
FIG. 1A
, schematically illustrating the flash memory structure.
FIG. 1C
, is a cross-sectional view of a portion of a substrate taken along a line II—II in
FIG. 1A
, schematically illustrating the flash memory structure.
In FIG.
1
A and
FIG. 1B
, a field oxide layer
104
formed by local oxidation process (LOCOS) is located on a semiconductor substrate
100
so as to define an active area
105
. A tunnel oxide layer
102
is formed on the active area
105
. A strip polysilicon layer
106
is formed over the substrate to cover an active area
105
. A strip polysilicon layer
110
and a strip dielectric layer
108
are formed to vertically cross over the strip polysilicon layer
106
. During the formation of the strip polysilicon layer
110
, the substrate
100
at a portion other than the strip polysilicon layer
110
is exposed by continuous etching. The polysilicon layer
106
therefore is also etched during the formation of the strip polysilicon layer
110
. A remaining portion of the polysilicon layer
106
becomes the polysilicon layer
106
a
. Also referring to
FIG. 1C
, an active area
105
a
, which originally is not covered by the strip polysilicon layer
106
, is over-etched during etching the polysilicon layer
106
. This over-etching effect causes that a trench
118
is formed in the substrate
100
. After an ion implantation process, a source line
120
, parallel to the strip polysilicon layer
110
, is formed in the substrate
100
. Since the source line
120
includes the trench
118
, it may cause a electrical discontinuity that further causes a poor conductivity of the source line
120
and an even causes a failure of the source line
120
. Moreover, since the field oxide layer
104
has a very large dimension, it is difficult to increase the memory integration.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a method for fabricating a flash memory with a simplified fabrication process. An electrical discontinuity of a source line is also effectively avoided.
In accordance with the foregoing and other objectives of the present invention, an improved method for fabricating a flash memory is provided. The improved method includes sequentially forming a tunnel oxide layer, a first polysilicon layer, and a silicon nitrite layer on a semiconductor substrate. A shallow trench isolation (STI) structure is formed in the substrate to define an active area. During the formation of the STI structure, the first polysilicon is simultaneously pre-patterned. The silicon nitride layer is removed. A dielectric layer and a second polysilicon layer are sequentially formed over the substrate. The second polysilicon layer, the dielectric layer, the first polysilicon layer, and the tunnel oxide layer are patterned to form a desired strip remaining structure on the substrate. A remaining portion of the first polysilicon layer serves as a gate of a memory cell. An interchangeable source/drain region is formed by ion implantation at each side of the gate structure, in which a source line parallel to the strip remaining structure.
In the foregoing, the invention uses the STI structure as the desired isolation structure. The device integration can effectively increase. The isolation structure in the conventional structure is a field oxide structure, which usually consumes available substrate area. Moreover, during the formation of the STI structure, the first polysilicon layer is simultaneously pre-patterned so that the fabrication process is simplified. The fabrication cost is reduced. Furthermore, since the first polysilicon has a uniform height over the substrate, when the first polysilicon layer is secondly patterned to form the gate structure, the substrate is not over etched at a certain portion. When a source line is formed, the source line has a uniform thickness. A conventional issue of discontinuity source line is effectively avoided. The source line contact resistance is effectively reduced.
REFERENCES:
patent: 5387534 (1995-02-01), Prall
patent: 5696019 (1997-12-01), Chang
Chaudhari Chandra
Huang Jiawei
J.C. Patents
United Semiconductor Corp.
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