Method for fabricating a flash memory

Details Method for fabricating a flash memory Method for fabricating a flash memory

1999-04-16

2001-04-10

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S594000

Reexamination Certificate

active

06214667

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 88100701, filed Jan. 18, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a flash memory.
2. Description of Related Art
Electrically erasable and programmable read only memory (EEPROM) is currently one the most widely used memory devices in personal computers and electronic equipment. A memory cell in an early, conventional EEPROM comprises a transistor with a floating gate performing write, erase, and data storage operations during electrical shut down. This conventional memory cell typically occupies a large surface area. The data access speed is between 150 ns to 200 ns. A recently developed memory cell has a faster data access speed ranging from about 70 ns to 80 ns. This memory cell is called a flash memory by Intel Co.
FIG. 1
is a schematic, cross-sectional view of a conventional flash memory. A conventional flash memory cell comprises a transistor with a floating gate. Referring to
FIG. 1
, a semiconductor substrate
100
is provided. A field oxide layer
101
is formed on the substrate
100
by local oxidation (LOCOS) to define an active area. A tunneling oxide layer
102
is formed on the substrate
100
. A floating gate
104
is formed on the tunneling oxide layer
102
. A control gate
108
is formed over the floating gate
104
. A dielectric layer
106
is formed between the control gate
108
and the floating gate
104
. An N-type source/drain region is formed in the substrate
100
beside the floating gate
104
. Oxide spacers
114
are formed on sidewalls of the floating gate
104
and the control gate
108
to protect the transistor with the floating gate from damage.
At present, a high-density flash memory fabrication becomes increasingly more important to satisfy requirements of high integration. However, in a conventional flash memory, the active area is defined by LOCOS isolation technology. The memory cell with a LOCOS isolation structure is hard to shrink the size so that device integration cannot be increased and also the capital expenditure is not reduced.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides an improved method for fabricating a flash memory. The method can minimize the cell size, increase device integration, and reduce capital expenditure for devices.
Another purpose of the invention is to provide an improved method for fabricating a flash memory so that tunnel efficiency of the flash memory is enhanced. The method can be applied in fabrication for a high-density flash memory.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for fabricating a flash memory. A semiconductor substrate is provided. A patterned gate oxide layer and a patterned mask layer are sequentially formed on the substrate. Hard material spacers are formed on sidewalls of the gate oxide layer and the mask layer. A trench is formed in the substrate using the mask layer and the hard material spacers as masks. An insulating layer is formed over the trench to form a shallow trench isolation structure and to expose the mask layer. The hard material spacers and the mask layer are removed to expose the gate oxide layer and a portion of the substrate. A tunneling oxide layer is formed on the exposed substrate. A defined first conductive layer is formed over the gate oxide layer and the tunneling oxide layer to serve as a floating gate. A dielectric layer is formed over the floating gate. A defined second conductive layer is formed over the dielectric layer to serve as a control gate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 6048768 (2000-04-01), Ding et al.
patent: 6114204 (2000-09-01), Ding et al .

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