Method for fabricating a flash memory

Details Method for fabricating a flash memory Method for fabricating a flash memory

1999-02-01

2000-11-28

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438296, 438594, H01L 218247

Patent

active

061534722

ABSTRACT:
A method for fabricating a flash memory is provided. The method contains sequentially forming a tunneling oxide layer, a polysilicon layer, and a silicon nitride layer on a semiconductor substrate. Patterning the silicon nitride layer, polysilicon layer, the tunneling oxide layer, and the substrate forms a trench in the substrate. A shallow trench isolation (STI) structure is formed to fill the trench up the silicon nitride layer. The silicon nitride layer is removed to expose the polysilicon layer and a portion of each sidewall of the STI structure. A polysilicon spacer is formed on each exposed sidewall of the STI structure. An upper portion of the STI structure is removed so as to expose a portion of each sidewall of the polysilicon layer. The polysilicon layer serves as a floating gate. A conformal dielectric layer and a top polysilicon layer are formed over the substrate. The top polysilicon layer, the dielectric layer, and the polysilicon layer are patterned to form a strip control gate, which covers the floating gate, that is a remaining portion of the polysilicon layer on the tunneling oxide layer.

REFERENCES:
patent: 5387534 (1995-02-01), Prall
patent: 5646059 (1997-07-01), Sheu et al.
patent: 5696019 (1997-12-01), Chang

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