Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-01
2002-07-23
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S216000, C438S226000
Reexamination Certificate
active
06423599
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor having dual gates in SOI (semiconductor on insulator) technology, for minimizing short-channel effects in the field effect transistor.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension junction
104
and a source extension junction
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension junction
104
and the source extension junction
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate electrode
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate electrode
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate electrode
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate electrode
118
and the gate dielectric
116
.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As the dimensions of the MOSFET
100
are scaled down further, the junction capacitances formed by the drain and source extension junctions
104
and
106
and by the drain and source contact junctions
108
and
112
may limit the speed performance of the MOSFET
100
. Thus, referring to
FIG. 2
, a MOSFET
150
is formed with SOI (semiconductor on insulator) technology. In that case, a layer of buried insulating material
152
is formed on the semiconductor substrate
102
, and a layer of semiconductor material
154
is formed on the layer of buried insulating material
152
. A drain
156
and a source
158
of the MOSFET
150
are formed in the layer of semiconductor material
154
. Elements such as the gate dielectric
116
and the gate electrode
118
having the same reference number in
FIGS. 1 and 2
refer to elements having similar structure and function. Processes for formation of such elements
116
,
118
,
152
,
154
,
156
, and
158
of the MOSFET
150
are known to one of ordinary skill in the art of integrated circuit fabrication.
In
FIG. 2
, the drain
156
and the source
158
are formed to extend down to contact the layer of buried insulating material
152
. Thus, because the drain
156
, the source
158
, and a channel region
160
of the MOSFET
150
do not form a junction with the semiconductor substrate
102
, junction capacitance is minimized for the MOSFET
150
to enhance the speed performance of the MOSFET
150
formed with SOI (semiconductor on insulator) technology.
In addition, referring to
FIGS. 1 and 2
, as the dimensions of the MOSFETs
100
and
150
are scaled down further, the occurrence of undesired short-channel effects increases, as known to one of ordinary skill in the art of integrated circuit fabrication. With short-channel effects, the threshold voltage of the MOSFET changes such that electrical characteristics of such a MOSFET become uncontrollable, as known to one of ordinary skill in the art of integrated circuit fabrication. In the prior art MOSFETs
100
and
150
of
FIGS. 1 and 2
, the gate dielectric
116
and the gate electrode
118
are formed on one surface of the channel region of the MOSFET. However, for controlling the electrical characteristics of the MOSFET, forming a gate dielectric and a gate electrode on a plurality of surfaces of the channel region of the MOSFET is desired to minimize undesired short channel effects.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, a field effect transistor is fabricated to have dual gates on two surfaces of the channel region of the field effect transistor formed in SOI (semiconductor on insulator) technology, to minimize undesired short channel effects.
In one embodiment of the present invention, in a method for fabricating a field effect transistor having dual gates, on a buried insulating layer in SOI (semiconductor on insulator) technology, a first layer of first semiconductor material is deposited on the buried insulating material. The first layer of first semiconductor material is patterned to form a first semiconductor island having a first top surface and a second semiconductor island having a second top surface. The first and second semiconductor islands are comprised of the first semiconductor material. An insulating material is deposited to surround the first and second semiconductor islands, and the insulating material is polished down until the first and second top surfaces of the first and second semiconductor islands are exposed such that sidewalls of the first and second semiconductor islands are surrounded by the insulating material.
In addition, a gate dopant is implanted into the second semiconductor island. A layer of back gate dielectric material is deposited on the first and second top surfaces of the first and second semiconductor islands. An opening is patterned through the layer of back gate dielectric material above the first semiconductor island such that a bottom wall of the opening is formed by the first top surface of the first semiconductor island. A second layer of second semiconductor material is grown from the exposed first top surface of the first semiconductor island and onto the layer of back gate dielectric material. A front gate dielectric is formed over a portion of the second layer of second semiconductor material disposed over the second semiconductor island. A front gate electrode is formed over the front gate dielectric. The second semiconductor island forms a back gate electrode, and a portion of the layer of back gate dielectric material under the front gate dielectric forms a back gate dielectric.
The present invention may be used to particular advantage when the first semiconductor material forming the first and second semiconductor islands are comprised of silicon and when the second layer of second semiconductor material is silicon epitaxially grown from the top surface of the first semiconductor island through the opening in the layer of back gate dielectric material.
In this manner, the back g
Choi Monica H.
Dang Trung
Kebede Brook
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