Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-24
2001-06-19
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06248620
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for fabricating field effect-controlled semiconductor components, such as e.g. but not exclusively MIS power transistors. Such semiconductor components contain a semiconductor substrate of a first conductivity type that is covered by a gate insulator layer. The essential method steps exhibited by the known methods are the production of a well of a second conductivity type in the semiconductor substrate and the production of a contact region of the first conductivity type in the well.
The smallest possible on resistances are striven for when fabricating MIS power transistors. On resistances of less than 3 m&OHgr; (in the TO220 housing) have already been achieved for planar MIS power transistors having reverse voltages of up to 100V. The channel resistance, the JFET resistance and the epitaxial resistance, i.e. the resistance of the semiconductor substrate through which the current flows after the channel to the drain terminal, each make up approximately one third of the on resistance. Since the epitaxial resistance cannot be influenced very much, it is necessary to reduce the channel resistance and the JFET resistance in order to reduce the on resistance.
In addition to reducing the on resistance, a high cell density and therefore a small cell size are striven for for components for high switching capacities. “Self-aligning” techniques are used nowadays for this purpose during the fabrication of the component. In this case, heavily doped polysilicon is used as the gate material and as a mask for the doping of source and drain. The gate serves as a mask for the doping, and the source and drain terminate exactly under the edge of the gate.
The actual fabrication of the cell with a small size is then carried out according to one of three techniques essentially used nowadays. In the first technique, a self-aligned channel is fabricated by diffusion after implantation via the edge of the polysilicon gate and an aligned contact hole is then produced on the semiconductor. The corresponding transistors are known as DMOS or DIMOS and SIPMOS transistors.
Since the threshold voltage, channel length and penetration depth mutually influence one another, however, in the case of the diffusion MOS transistors, the parameters cannot be optimized individually. In addition, the charge carrier concentration decreases in the channel between the source and the drain in the transistors fabricated by diffusion. However, the maximum concentration of the charge carriers (at the source) determines, for its part, the threshold voltage of the transistor, with the result that the channel length cannot be reduced to significantly below 1 &mgr;m.
In a second technique, a double diffused (DMOS) FET is fabricated and a self-aligned contact hole is provided with the aid of the known “spacer” technology. The self-aligned contact hole fabricated using spacer technology enables the spacing of the contact hole from the gate to be reduced to approximately 0.5 &mgr;m without a high requirement being made on the alignment. This results in a geometrical length from the contact hole up to the end of the channel at the drain of approximately 1.5 &mgr;m.
A further reduction in the channel length to below 1 &mgr;m is not possible using this method.
Finally, in a third method according to the prior art, the channel and the contact hole are produced by traditional methods (without self-alignment) by aligning the corresponding masks with one another.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for fabricating a field effect-controlled semiconductor component which overcomes the above-mentioned disadvantages of the prior art methods of this general type, in which a field effect-controllable semiconductor component is fabricated with the smallest possible on resistance which can be implemented in a technically simple and cost-effective manner.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a field effect-controllable semiconductor component, which includes:
providing a semiconductor substrate of a first conductivity type having a surface;
producing a gate insulator layer on the surface of the semiconductor substrate;
producing a semiconductor layer having a first predetermined thickness on the gate insulator layer;
reducing the semiconductor layer in a predetermined region to obtain a residual layer having a second predetermined thickness; and
producing a well of a second conductivity type in the semiconductor substrate by implanting impurity atoms with the semiconductor layer acting as an implantation barrier outside a predetermined region during the producing step of the well.
The production of a semiconductor layer having a relatively large thickness on the insulator layer serves as an implantation barrier outside the predetermined region when the well of a second conductivity type is produced in the semiconductor substrate by the implantation of first impurity atoms. The “superfluous” portion of the semiconductor layer is removed within the predetermined region. As a result of the smaller thickness of the semiconductor layer in the predetermined region, the depth of the well in the semiconductor substrate can be set precisely during implantation. The edge of the well can also be precisely defined by this method; no impurity atoms penetrate the semiconductor substrate below the relatively thick semiconductor layer above the substrate outside the predetermined region. In this way, it is possible to fabricate shallow and sharply delimited wells in the semiconductor substrate. On account of the small depth of the well, the channel length can be set to be smaller, with the result that the channel resistance decreases. Moreover, two adjacent cells can be disposed nearer to one another. The resistance of the JFET between two adjacent cells is reduced.
Preferably, in the method according to the invention, in order to produce the semiconductor layer on the gate insulator layer, a first semiconductor layer is produced on the gate insulator layer, an intermediate insulator layer is produced on at least a portion of the first semiconductor layer, a second semiconductor layer is produced on the intermediate insulator layer, with the result that the second semiconductor layer is partly in contact with the first semiconductor layer, and the first semiconductor layer corresponds to the residual layer in the predetermined region.
In a further preferred embodiment of the method, before the production of the contact region, a first spacer is produced as an implantation barrier on the residual layer, with the result that the spacing of the contact region from the edge of the well is predetermined. The width of the spacer enables the length of the conductive channel of the semiconductor component to be set precisely.
Preferably, after the production of the contact region, a second spacer is additionally produced as an etching barrier on the semiconductor substrate. As a result, the spacing of the contact hole from the edge of the well can also be predetermined and the extent of the contact region, i.e. of the source zone, can thus be set precisely.
One advantage of the invention is that with the reduction in the channel resistance by way of the shortening of the channel length, the cell spacing in the component can also be reduced and a power element is thus created which has smaller dimensions of the individual cells and hence a higher cell density. As a result, more cells can be fabricated on the same area and be connected in parallel, which leads to a further reduction in the on resistance.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a field effect-controlled semiconductor component, it is nevertheless not intended to be limited to the details shown, since various modification
Gassel Helmut
Larik Joost
Strack Helmut
Bowers Charles
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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