Method for fabricating a DRAM capacitor

Details Method for fabricating a DRAM capacitor Method for fabricating a DRAM capacitor

2000-03-06

2001-07-17

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S254000, C438S255000

Reexamination Certificate

active

06261900

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor memory device, and more particularly to a method for fabricating a bowl-shaped capacitor for a dynamic random access memory (DRAM).
2. Description of the Prior Art
Please refer to
FIGS. 1A through 1F
, wherein the cross-sectional views of a conventional method for fabricating a DRAM cell are depicted in sequence.
Referring to
FIG. 1A
, a P-type semiconductor substrate
10
having a shallow trench isolation STI and transistors comprising gates G
1
, G
2
, G
3
and N-type source and drain regions
12
a,
12
b,
12
c
is shown, wherein the gates G
1
, G
2
, G
3
comprise an oxide layer
15
, a polosilicon layer
16
, a tungsten silicide layer
18
, a silicon nitride masking layer
20
, and a silicon nitride spacer
14
.
Referring to
FIG. 1B
, a first insulating layer
24
, for example, an oxide layer is formed on the semiconductor substrate
10
. Subsequently, a first opening
26
for exposing the drain region
12
b
is formed by etching the first insulating layer
24
. As shown in
FIG. 1C
, a bit line BL comprising a polysilicon layer
32
and a tungsten silicide layer
33
is then formed in the first opening
26
.
Please refer to
FIG. 1D. A
second insulating layer
34
, such as an oxide layer is globally formed on the first insulating layer
24
. Subsequently, a second opening
35
for exposing the source region
12
c
is formed by etching the second and the first insulating layers
34
and
24
.
Referring to
FIG.1E
, a conventional stacked capacitor is then formed by the following steps: forming a contact
51
in the second opening
35
; forming a bottom electrode (conducting plate)
50
on the contact
51
; forming a dielectric layer
52
on the bottom electrode
50
; and forming an upper electrode (conducting plate)
54
on the dielectric layer
52
. As well known by those persons skilled in this field, the most important parameters effecting the charges stored in the capacitor are the area of the capacitor plates, the dielectric constant, and the thickness of the insulator. Therefore, many approaches have been developed to increase the area of the electrodes by using different structures for the stacked capacitors to. For example, a crown capacitor is described in the U.S. Pat. No. 5,891,768, and a branch capacitor recited in the U.S. Pat. No. 5,904,522. However, the processes mentioned above are complicated, as etching and depositing steps must be very precise. Thus, the complexity and the cost of the processes are increased.
SUMMARY OF THE INVENTION
Accordingly, the object of the present invention is to provide a simple and inexpensive method for fabricating a capacitor in a DRAM cell, wherein the area of the electrodes is large.
To attain the above-mentioned object, a method for fabricating a DRAM capacitor is provided. The method comprises the following steps: (a) providing a semiconductor substrate having a transistor and a bit line; (b) forming a lower insulating layer covering the transistor and the bit line, an etching stop layer, and an upper insulating layer;(c) forming a photoresist layer having an opening on the upper insulating layer;(d) forming a bowl-shaped opening by wet etching the upper isolating layer by the pattern of the opening in the photoresist layer; forming a contact window by dry etching the etching stop layer and the lower isolating layer by the pattern of the bowl-shaped opening and the opening in the photoresist layer; (e) removing the photoresist layer; (f) forming a first conducting layer on the upper isolating layer and filling the contact window; and (g) forming a bowl-shaped capacitor by forming a dielectric layer and a second conducting layer on the first conducting layer.


REFERENCES:
patent: 5891768 (1999-04-01), Figura et al.
patent: 5904522 (1999-05-01), Chao
patent: 6013733 (2000-01-01), Lee et al.
patent: 6015734 (2000-01-01), Huang et al.

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