Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2005-01-11
2005-01-11
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S244000, C438S255000, C438S386000, C438S387000, C438S398000, C257S301000, C257S303000, C257S309000
Reexamination Certificate
active
06841443
ABSTRACT:
A method for fabricating a deep trench capacitor for dynamic memory cells in which a trench is etched into the depth of a semiconductor substrate, and wherein the interior of the trench is provided with a doping and a dielectric and is filled with a conductive material as an inner electrode. The inner electrode and the dielectric are etched back within a collar region, and a collar is formed using a collar process comprising a collar oxide deposition and etching back of the collar oxide on the substrate surface and in the trench as far as the inner electrode, after which the inner electrode is completed by further steps of depositing and etching back conductive layers. Prior to the doping a masking layer is applied to the collar region of the trench, and this masking layer is removed again before the collar process. Before the dielectric is applied the surface of the lower regions of the trench outside the collar region a layer of grains of conductive material is applied.
REFERENCES:
patent: 5877061 (1999-03-01), Halle et al.
patent: 5981350 (1999-11-01), Geusic et al.
patent: 6025225 (2000-02-01), Forbes et al.
patent: 6159874 (2000-12-01), Tews et al.
patent: 6448131 (2002-09-01), Cabral et al.
patent: 6537872 (2003-03-01), Tsao et al.
patent: 6555430 (2003-04-01), Chudzik et al.
patent: 6734077 (2004-05-01), Forster et al.
patent: 10100582 (2002-07-01), None
patent: 02056369 (2002-01-01), None
Saida et al., Embedded Trench DRAMs for Sub-0.10-μm Generation by Using Hemispherical-Grain Technique and LOCOS Collar Process,IEEE Trans. Semiconductor Manufacturing, 14 (Aug. 2001) 196.
Krasemann Anke
Temmler Dietmar
Baker & Botts LLP
Lebentritt Michael S.
Wilson Christian D.
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