Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-09-22
1999-11-23
Utech, Benjamin
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438255, 438745, H01L 128242
Patent
active
059899522
ABSTRACT:
A method for fabricating a DRAM cell having a crown-type capacitor over a semiconductor substrate is disclosed. The method includes steps of: (a) forming a transistor over the semiconductor substrate; (b) forming an insulating layer over the transistor; (c) selectively etching the insulating layer to form a contact opening; (d) forming a first conducting layer over the insulating layer and filling into the contact opening; (e) forming an etching stop layer and a mask layer over the first conducting layer; (f) pattering the mask layer to form a plurality of openings; (g) forming a dielectric spacer on the sidewall of the mask layer, and removing exposed portions of the etching stop layer; (h) anisotropically etching the mask layer and the first conducting layer by using the dielectric spacer as a mask, to expose, respectively, the etching stop layer and the insulating layer; (i) removing uncovered etching stop layer to expose the first conducting layer; (j) anisotropically etching the first conducting layer to a predetermined depth by using the dielectric spacer as a mask, thereby forming a crown-type storage electrode; (k) removing the dielectric spacer and the etching stop layer; (l) forming a dielectric layer over exposed portions of the storage electrode; and (m) forming a second conducting layer as an opposite electrode over the dielectric layer.
REFERENCES:
patent: 5543345 (1996-08-01), Liaw et al.
patent: 5700731 (1997-12-01), Lin et al.
patent: 5792689 (1998-08-01), Yang et al.
Cheng Jia-Shyong
Jen Tean-Sen
Lin Chi-Hui
Wang Shiou-Yu
Bednarek Michael D.
Nanya Technology Corporation
Umez-Eronini Lynette T.
Utech Benjamin
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