Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-06
2001-07-24
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S269000, C438S138000
Reexamination Certificate
active
06265269
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a power device in a trench, more particularly, to a method for fabricating a concave bottom oxide to serve as an insulating layer of a power device in a trench.
BACKGROUND OF THE INVENTION
As a conventional power MOSFET, a DMOS (Double diffusion MOS) structure has been generally used. However, such a structure has the following problems when increasing the integration density by applying a fine pattern structure thereon.
First, a diffusion length of a lateral direction for forming a base region is limited to a pitch of design layout. Second, a parasitic JFET (Junction FET) formed between contiguous base regions narrows a path through which a current vertically flows, thereby to increase a resistance component of a buffer layer.
The tendencies of the problems are enhanced when the design pitch is set to be small. As a result, since an optimum value is present in the layout, a decrease in on-resistance may be limited even if the integration density is increased. However, when the area of an element is increased to decrease the on-resistance, a production cost may be increased, and problems such as an unstable operation of the element or parasitic oscillation caused by parallel connection may caused.
For this reason, a MOSFET having a gate formed in a trench, a source formed above the gate, and a substrate used as a drain has been developed. To realize trench-type MOSFET in a high integration density, the gate oxide layer in the trench must be thin in order to enhance current drive, that is to decrease the on-resistance. The thinning of the gate oxide in the trench has highly potential risks, that is a very high current density will punch through the gate oxide layer at the bottom of the trench. For solving this issue, a thick bottom gate oxide is formed in the trench instead of this gate oxide layer.
In the conventional technology for fabricating a power MOS device, the power MOS device is fabricated in a trench in a semiconductor substrate and the source/drain regions are fabricated in the trench, too. Before the power MOS device is fabricated in the trench, a bottom oxide layer is firstly formed in the trench. The source/drain regions and the gate are then formed in the trench and the bottom oxide layer in the trench is served as an insulating layer of the power MOS device. In prior art, the bottom oxide layer is planar and the corner between the bottom oxide layer and the trench has an angle about 90 degrees. Besides, the source or drain region of a trench power MOS is formed on the bottom oxide layer in the trench and a spike effect of the trench power MOS device often occurs on the perpendicular corner between the sidewall of the trench and the bottom oxide layer.
Thus, changing the perpendicular corner between the sidewall of the trench and the bottom oxide layer in the trench into a non-perpendicular corner can prevent a trench power MOS device from a current leakage from the source/drain regions of the trench power MOS device. In other word, it is not necessary to have a sharp trench to prevent the corner from forming a spike.
Therefore, what is needed is to form a bottom oxide layer having a concave surface and the bottom oxide layer is served as an insulating layer of a trench power MOS device.
SUMMARY OF THE INVENTION
A method for forming a concave bottom oxide layer in a trench, comprising: providing a semiconductor substrate; forming a pad oxide layer on the semiconductor substrate; forming a silicon nitride layer on the pad oxide layer; etching the silicon nitride layer, the pad oxide layer and the semiconductor substrate to form the trench in the semiconductor substrate; depositing a silicon oxide layer to refill into the trench and cover on the silicon nitride layer, wherein the silicon oxide layer has overhang portions at corners of the trench; anisotropically etching the silicon oxide layer to form a concave bottom oxide layer in the trench; etching the silicon oxide layer to remove the silicon oxide layer on the silicon nitride layer and the sidewalls of the trench; removing the silicon nitride layer and the pad oxide layer.
REFERENCES:
patent: 5326711 (1994-07-01), Malhi
patent: 5532179 (1996-07-01), Chang et al.
patent: 5648283 (1997-07-01), Tsang et al.
patent: 5888880 (1999-03-01), Gardner et al.
patent: 5897343 (1999-04-01), Mathew et al.
patent: 5937296 (1999-08-01), Arnold
patent: 6114194 (2000-09-01), Hsu
patent: 6133099 (2000-10-01), Sawada
Chen Chien-Hung
Chen Juinn-Sheng
Lin Ching-Shun
Wu Chih-Ta
Bowers Charles
Mosel Vitelic Inc.
Nath & Associates
Novick Harold L.
Smoot Stephen W.
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