Method for fabricating a capacitor of a DRAM with an HSG layer

Details Method for fabricating a capacitor of a DRAM with an HSG layer Method for fabricating a capacitor of a DRAM with an HSG layer

1998-12-04

2000-04-18

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438665, H01L 218242

Patent

active

060514647

ABSTRACT:
A method for fabricating a capacitor including a storage capacitor of a dynamic random access memory (DRAM) starts with forming a dielectric layer and then a mask on a provided substrate, wherein the provided substrate contains a pre-formed field effect transistor (FET). By patterning the dielectric layer, a contact window is formed to expose the source/drain regions on the provided substrate. Then, a conducting layer is formed to cover the mask and fill the contact window, wherein the conducting layer is electrically connected to the source/drain region. A hemispherical-grained silicon (HSG) layer is formed on the conducting layer, wherein the silicon grains are respectively surrounded by spacers formed in a follow-up process. The HSG layer and a portion of the conducting layer are removed by performing an anisotropic etching process that uses the spacers as masks. The remains of the conducting layer, a multi-micro-cylinder structure, serves as the storage electrode of a capacitor. A dielectric layer and then, another conducting layer are formed on the multi-micro-cylinder structure after the spacers are removed.

REFERENCES:
patent: 5821142 (1998-10-01), Sung et al.
patent: 5837581 (1998-11-01), Cheng
patent: 5933742 (1998-10-01), Wu

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