Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-13
2001-02-06
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S396000, C438S397000
Reexamination Certificate
active
06184078
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for fabricating a capacitor for a high density dynamic random access memory (DRAM).
BACKGROUND OF THE INVENTION
With the continuous increase in integration of DRAM devices, respective components, for example, cell capacitors to store data, in each DRAM device are further reduced in each dimension. Nevertheless, the cell capacitors must have a sufficient enough capacitance to store data. Consequently, to increase the capacitance of a capacitor which is formed in a limited area, technological studies have been undertaken to increase the effective area of such capacitors. Most storage nodes of cell capacitors which are formed in high density DRAM devices of 256 Megabits and more have three-dimensional structures such as a cylindrical, cup, crown, or fin-shaped structure.
Several methods to increase capacitance have been published. Of them, particularly, a hemispherical grain silicon (HSG) forming method is disclosed in U.S. Pat. No. 5,622,889. If that method is applied to fabrication of DRAM cell capacitors, the capacitor storage nodes have to be further miniaturized in the limited area because a constant interval between the storage nodes should be maintained. The miniaturization of capacitor storage nodes makes it difficult to provide an overlapping margin (depicted by a symbol “M” in
FIG. 1C
) between the capacitor storage node and the buried contact pad or the buried contact in fabrication of DRAM devices.
In addition, as the degree of integration in DRAM devices is further increased, size of the capacitor storage node or the buried contact pad for electrical connection with the storage node junction must be further miniaturized. For this reason, it is also very difficult to overlap the capacitor storage node with the capacitor contact pad or the buried contact in fabrication of DRAM devices.
SUMMARY OF THE INVENTION
The present invention is intended to solve the problem, and it is an object of the invention to provide a method for fabricating a DRAM cell capacitor in which a storage node is formed on a buried contact pad in self-alignment.
It is another object of the present invention to provide a method for fabricating a DRAM cell capacitor in which a storage node and a buried contact pad are sufficiently overlapped with each other.
According to one aspect of the present invention, a method for fabricating a capacitor is applicable to a high density dynamic random access memory (DRAM) device on a semiconductor substrate which has a buried contact pad within a first insulator layer formed thereon. This method comprises forming a second insulator layer on the first insulator layer, including on the buried contact pad. A third insulator layer is formed thereon. An etching stopper layer is next formed on the third insulator layer. Sequentially, a fourth insulator layer and a first polysilicon layer are formed on the etching stopper layer. A masking layer is formed on the first polysilicon layer to define a storage node. The first polysilicon layer and the fourth insulator layer are sequentially etched using the masking layer until the etching stopper layer is exposed, so as to form a top via hole. A sidewall spacer is formed on the sidewall of the top via hole. After removing the masking layer, the etching stopper layer and the second and third insulator layers are sequentially etched using a combination of the first polysilicon layer and the sidewall spacer as a mask until the contact pad is exposed, so as to form a bottom via hole beneath the top via hole. A second polysilicon layer is deposited, filling up the bottom and top via holes. The semiconductor substrate is planarized by a chemical mechanical polishing (CMP) procedure until the third insulator layer is exposed. Finally, the third insulator layer is etched to form the storage node wherein the sidewall spacer and the second polysilicon layer are in self-alignment.
According to the other aspect of the present invention, a method for fabricating a capacitor for a high density dynamic random access memory (DRAM) device on a semiconductor substrate having a buried contact pad within a first insulator layer formed thereon, comprises forming a second insulator layer on the first insulator layer, including on the buried contact pad. A third insulator layer is formed thereon. An etching stopper layer is next formed on the third insulator layer. A fourth insulator layer is formed on the etching stopper layer. On the fourth insulator layer, a masking layer is formed to define a storage node. The fourth insulator layer is etched, using the masking layer, until the etching stopper layer is exposed, so as to form a top via hole. After removal of the masking layer, a first polysilicon layer is deposited on the fourth insulator layer filling the top via hole. The first polysilicon layer is etched back in order that a sidewall spacer is formed on the interior sidewall of the top via hole and a part of the first polysilicon layer remains on an upper surface of the third insulator layer. The etching stopper layer and the second and third insulator layers are etched, using a combination of the part and sidewall spacer of the first polysilicon layer as a mask, until the contact pad is exposed, so as to form a bottom via hole beneath the top via hole. A second polysilicon layer is deposited filling up the bottom and top via holes. The semiconductor substrate is planarized until the fourth insulator layer is exposed. The fourth insulator layer is etched to form the storage node, having a cylindrical shape and having the sidewall spacer and the second polysilicon layer in self-alignment.
REFERENCES:
patent: 5622889 (1997-04-01), Yoo et al.
patent: 5631185 (1997-05-01), Kim et al.
patent: 5786250 (1998-07-01), Wu et al.
patent: 5872041 (1999-02-01), Lee et al.
patent: 5926709 (1999-07-01), Aisou et al.
patent: 5930623 (1999-07-01), Wu
patent: 6037234 (1999-07-01), Hong et al.
Bae Yong-cheol
Yoon Sei-seung
Bowers Charles
Chen Jack
Jones Volentine, L.L.C.
Samsung Electronics., Ltd.
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