Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-05
2001-08-07
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S264000, C438S266000, C438S589000, C438S594000
Reexamination Certificate
active
06271088
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a vertical split gate flash memory cell, particularly, a vertical split gate flash memory cell buried in a silicon substrate, with characteristics of high coupling ratio, high density and low programming voltage.
2. Background of the Invention
For the past decade, electrically erasable programmable read only memory (EEPROM) devices have been one of the most popular and well-developed memory devices in the semiconductor industry. The advantages of the EEPROM over a conventional ROM device are its ability to electrically write, save and erase data.
Please refer to
FIG. 1
of a cross-sectional conventional split gate flash memory cell
30
. As shown in
FIG. 1
, the conventional split gate flash memory cell
30
comprises a gate oxide layer
32
, a floating gate
34
, a control gate
38
, a drain
42
, and a source
44
. The control gate
38
is a step structure whereby its lower step end controls a selective channel
31
. The upper end of the step structure of the control gate
38
is formed atop the floating gate
34
with a dielectric layer
36
, usually of oxide-nitride-oxide (ONO), separating the two gates
34
,
38
.
The flash memory device
30
is programmed when hot electrons from the selective channel
31
are injected into the floating gate
14
by tunneling, via the gate oxide layer
32
, according to scattering or other physical mechanisms to thereby increase the threshold voltage of the flash memory cell
30
. Erasure occurs when a negative voltage is applied to the control gate
38
to expel the electrons trapped in the floating gate
34
. After the electrons are expelled, the threshold voltage of the flash memory cell
30
is restored to its original condition.
Although the split gate flash memory cell solves the problem of over erasing in the conventional flash memory device, the coupling ratio of the split gate flash memory cell is insufficient, leading to a reduced erasing speed or incomplete erasure. Moreover, high-speed, compact, and energy-efficient electronic devices are continually demanded by customers. To satisfy such demands, many types of high-speed/density flash memory devices have been disclosed. For example, a planar step-structure split gate flash memory cell has been developed which involves the use of both an ultra short channel and a ballistic channel hot electrons (CHE) mechanism with the advantages of low program voltage and low energy consumption.
Please refer to
FIG. 2
of a cross-section of a conventional step-structure split gate device
50
. As shown in
FIG.2
, the step-structure split gate device
50
comprises a control gate
58
and a floating gate
54
located on a silicon substrate
60
. The floating gate
54
is located on a step structure, and includes a horizontal channel of 25 nm in length and a vertical channel of 25 nm in depth. A gate oxide layer
52
of 9 nm thick is positioned between the control gate
58
and the silicon substrate
60
, as well as between the floating gate
54
and the silicon substrate
60
. An N
+
source region
64
is formed adjacent to the control gate
58
on the surface of the silicon substrate
60
, and an N
+
drain region
62
is located adjacent to the floating gate
54
on the surface of the silicon substrate
60
. An N-type extended region
63
is located beneath the floating gate
54
adjacent to the N
+
drain region
62
, and a P-type doped area
65
is formed at the bend of the step structure to provide a high field region. Hot electrons
71
enter the depleted high field region at one end of the channel beneath the control gate
58
, and directly travel towards the floating gate
54
. During the injection of the hot electrons
71
into the floating gate
54
, either the Coulomb effect or phonon scattering rarely occurs.
In U.S. Pat. No. 6,074,914, Ogura invents a method of making a sidewall split gate flash memory cell which possesses the high speed CHE programming feature, whereby a short channel of 25 to 60 nm is used. In U.S. Pat. No. 6,133,098, Ogura et al. present a method of making a high-density sidewall split gate flash memory cell, which includes the following features:
(1) use of a high density dual-bit cell;
(2) use of the ballistic CHE mechanism, to allow for a low writing current and low writing voltage; and
(3) a third level polysilicon control gate to override coupling of a word line with a floating gate.
However, the conventional photolithographic process makes difficult the manufacturing of a sidewall floating gate with an ultra short channel of 50 nm long. Therefore, a polysilicon layer is generally etched with a reactive ion etching method to form the polysilicon sidewall floating gate along the sidewall of the control gate. By the use of this method, the thickness of the base portion of the floating gate, also called the floating gate channel, is not easily regulated.
SUMMARY OF THE INVENTION
The purpose of the present invention is to provide a method of making a buried split gate flash memory device with an ultra short channel and having the characteristics of a larger coupling ratio, higher packing density and lower programming voltage.
Another purpose of the present invention is to provide a method of making a vertical split gate flash memory device to produce a controlled thickness of the floating gate as well as to obtain a lower operating voltage for the memory cell.
One other purpose of the present invention is to provide a method of making a dual-bit vertical split gate flash memory device on a SOI substrate, to achieve ultra-high density for the electronic device.
In the present invention, the method of making a buried split gate flash memory device involves: (1) forming a cap layer on top of a silicon substrate; (2) etching the silicon substrate to form a trench containing a sidewall; (3) forming a spacer over the sidewall; (4) etching the bottom of the trench to form a second trench containing a second sidewall; (5) performing an ion implantation process to form a source in the silicon substrate; (6) forming a dielectric layer on the bottom of the second trench; (7) forming a tunneling oxide layer over the second sidewall; (8) forming a control gate layer over the first dielectric layer and filling in the second trench; (9) removing the first spacer; (10) forming a second dielectric layer on the control gate layer; (11) forming a second tunneling oxide layer on the first sidewall; (12) forming a floating gate layer on the second dielectric layer, wherein the top of the floating gate layer is slightly lower than that of the silicon substrate; (13) forming a third dielectric layer on the floating gate layer; (14) removing the cap layer; and (15) forming a drain to replace the cap layer.
In the present invention, a CVD process is used to form both the control gate and the floating gate of the split gate flash memory device, whereby a desired floating gate channel length is effectively produced. For instance, a floating gate channel length three to four times greater than the electron mean free path can be achieved.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 6008089 (1999-12-01), Hong
patent: 6040210 (2000-03-01), Burns, Jr. et al.
Liu Chih-Cheng
Wu De-Yuan
Booth Richard
Hsu Winston
United Microelectronics Corp.
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