Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-30
2001-11-20
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000
Reexamination Certificate
active
06319770
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a method for fabricating a bottom electrode of a dynamic random access memory (DRAM) capacitor. More specifically, the present invention relates to a method that can enlarge the surface area of the bottom electrode of a DRAM capacitor.
2. Description of the Related Art
A DRAM cell is constructed of a MOS transistor and a capacitor, wherein the charge storage ability of the capacitor is utilized to store information. Because of charge leakage paths, such as the inverse bias leakage path of a PN junction, it is necessary to recharge or discharge the capacitor of a cell at regular intervals to keep the stored information correct. This is called refreshing. The longer the refresh interval, the more stable the stored information. Furthermore, the power consumption of the DRAM cell is less.
One way to prolong the refresh interval is to increase the capacitance of the capacitor. This can be accomplished by enlarging the surface area of the bottom electrode of the capacitor.
FIG. 1
is a cross-sectional view of a capacitor using a fin structure to increase the surface area of the bottom electrode. The fin structure has an inter-poly dielectric layer
12
and a poly plug
14
formed therein to act as a node contact. A bottom electrode superposing on the poly plug
14
has a main stem
16
and an annular ring
18
. The main stem
16
and the annular ring
18
are usually made of amorphous silicon doped with phosphorous. An inter-plate dielectric layer
22
electrically separates the top electrode
20
and the bottom electrode. As shown in
FIG. 1
, the annular ring
18
enlarges the surface area of the bottom electrode.
As illustrated in
FIG. 2
, hemispherical grains can be applied to the fin structure of the bottom electrode in
FIG. 1
to further enlarge the surface area. The distended surfaces of the hemispherical grains increase the surface area of the bottom electrode. The larger the diameters of the hemispherical grains, the larger the capacitance.
The diameter of a hemispherical grain has strong correlation with the impurity concentration of the amorphous silicon at the location where the hemisphere grain grows. The lower the impurity concentration, the larger the diameter of the hemispherical grain and the larger the capacitance of the capacitor. However, a bottom electrode with hemispherical grains having large diameters has an increased probability of contacting and shorting with an adjacent bottom electrode. Further, if the impurity concentration of the amorphous silicon is lessened to grow large hemispherical grains, the depletion region of the surface of the hemispherical grains will be enlarged. This result decreases the capacitance.
SUMMARY OF THE INVENTION
Therefore, a major object of the present invention is to provide a method for fabricating a bottom electrode having a fin structure with hemispherical grains without the aforementioned disadvantages.
The present invention achieves the above-indicated object by providing a method for fabricating a bottom electrode of a dynamic random access memory (DRAM) capacitor. First, a first sacrificial layer, an intermediate layer and a second sacrificial layer are sequentially formed on a substrate. Then, an aperture is formed on the first sacrificial layer, the intermediate layer and the second sacrificial layer. After that, an annular groove is formed in the inner circumferential surface of the aperture by removing a fixed depth of the intermediate layer. Then, the aperture and the annular groove are filled with a first amorphous silicon layer, a second amorphous silicon layer and a third amorphous silicon layer. The second amorphous silicon layer has a lower impurity concentration than those of the first amorphous silicon layer and the third amorphous silicon layer do. The first amorphous silicon layer and the second amorphous silicon layer both fill into the annular groove and form an annular ring. Next, the first sacrificial layer and the second sacrificial layer are removed to reveal the first amorphous silicon layer. Next, a predetermined depth of the first amorphous silicon layer is removed to reveal the second amorphous silicon layer. Then, the intermediate layer is removed to reveal the first amorphous silicon layer at the annular ring. Finally, a plurality of hemispherical grains are formed on the first amorphous silicon layer and the second amorphous silicon layer.
The advantage of the present invention is to dramatically increase the capacitance of the capacitor. When the hemispherical grains are being formed, the sidewall of the annular ring is the closest portion of the bottom electrode to the adjacent bottom electrode Because the sidewall of the annular ring is covered with the first amorphous silicon layer having a higher impurity concentration covering, the grain size of hemispherical grains at the sidewall of the annular ring will be smaller, thereby preventing the occurrence of electrical shorting. Furthermore, since most surface of the bottom electrode is made of the second amorphous silicon layer having a lower impurity concentration, the grain size formed thereon will be larger, thereby increasing the surface area of the bottom electrode. By this means, the capacitance is increased. In addition, the impurity in the third amorphous silicon layer is diffused into the hemispherical grains by means a subsequent thermal treatment process, thereby decreasing the depletion region at the surfaces of the hemispherical grains.
REFERENCES:
patent: 5879987 (1999-03-01), Wang
patent: 6063660 (2000-05-01), Tseng et al.
patent: 6100129 (2000-08-01), Tu et al.
patent: 6114201 (2000-09-01), Wu
patent: 6162680 (2000-12-01), Lou
patent: 6218230 (2001-04-01), Fujiwara et al.
Darby & Darby
Nguyen Tuan H.
Taiwan Semiconductor Manufactruing Co., LTD
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