Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-08-30
2003-12-30
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S269000, C438S222000, C438S481000
Reexamination Certificate
active
06670244
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for fabricating a body region for a vertical MOS transistor arrangement in a semiconductor body which has a reduced on resistivity. Shortening the channel length of the MOS structure is a significant factor for optimizing the on resistance of MOS transistor arrangements. The minimum possible channel length and thus the minimum possible channel resistance is defined by the so-called punch strength. The charge carrier concentration in the body region between the source region and the drain region must be high enough that, up to the maximum allowed drain-source voltage, the space charge zones at the pn-junctions of the source region/body region and the body region/drain region do not touch, since otherwise an impermissibly high current flows. On the other hand, however, the maximum charge carrier concentration of the body region in the channel region is defined by the threshold voltage, which is usually predetermined in customary MOS transistor arrangements.
SUMMARY OF THE INVENTION
It is an object of the present invention, therefore, to provide a method for fabricating a vertical MOS transistor arrangement whereby it is possible to achieve a reduction in the channel length of the transistor arrangement with the breakdown voltage remaining the same, and hence a reduction in the on resistivity.
A description is given of a method for fabricating a body region of the first conduction type for a vertical MOS transistor arrangement in a semiconductor body, the body region comprising at least one channel region, which is arranged between a source region of the second conduction type and a drain region of the second conduction type and adjoins a gate electrode. In this case, the body region and the source region extend from a first surface of a semiconductor body into the semiconductor body, and the drain region extends from a second surface of the semiconductor body into the semiconductor body. In this case, by way of example, the gate electrode can either be arranged on the first surface of the semiconductor body or it can also be arranged in a gate trench extending in the vertical direction from the first surface of the semiconductor body into the semiconductor body.
According to the invention, at least two implantations of a doping material of the first conduction type into the semiconductor body are carried out. The first implantation is carried out in such a way that the implantation maximum is arranged set back from the channel region. In other words, if the gate electrode of the transistor arrangement is arranged in the region of the first surface, and if the channel region thus also lies in the region of the surface, then the first implantation is carried out in such a way that the implantation maximum lies in the semiconductor body set back from the first surface. For the case of a gate electrode which is arranged in a vertical gate trench, the implantation is carried out in such a way that the implantation maximum is arranged set back in the lateral direction from the channel region which extends along the gate electrode in the vertical direction in the body region. In this case, it may also be provided at the same time that the implantation maximum is likewise arranged within the semiconductor body set back from the first surface.
A second implantation of doping material of the first conduction type is carried out in such a way that the implantation maximum of the second implantation lies in the semiconductor body below the implantation maximum of the first implantation, but the dose of the second implantation is lower than the dose of the first implantation. An outdiffusion of the implanted doping material is carried out, in which case, depending on the conditions, an outdiffusion may be provided after each individual implantation or, alternatively, an outdiffusion is carried out only after all the implantations have been carried out.
In this case, the specifications for the implantation and outdiffusion of the doping material can be set in such a way that a gradient of the doping concentration in the direction toward the channel region can be obtained in the region of the first implantation of the doping material. What can thus be achieved is that a lower concentration of the doping material and thus a lower charge carrier concentration, too, are present in the channel region, as a result of which the threshold voltage of the MOS transistor arrangement is not significantly altered. On the other hand, however, by virtue of the greater concentration of the doping material which is arranged set back from the channel region, an increase will be obtained in the charge carrier concentration in a partial region of the body region, which ensures the punch strength of the MOS transistor arrangement.
The second implantation having a lower doping concentration below the first implantation, that is to say in a region of the body region which faces the drain region and generally adjoins a drift region, has the effect that, in the off-state case of the MOS transistor arrangement, a partly mutual depletion of this region of the body region and of the adjoining drift region of the drain region can be achieved through a compensation effect. Consequently, in the case of the arrangement, it is possible to obtain an increase in the breakdown voltage. Conversely, with the breakdown voltage remaining the same, the thickness of the drift region can be reduced and the doping of the drift region can be increased, which leads to a reduction of the on resistance.
The method according to the invention thus makes it possible, in a simple manner, to produce an optimized doping profile of a body region of a vertical MOS transistor arrangement which allows a reduction of the on resistivity of the MOS transistor arrangement. Insofar as is desirable, it is also possible to achieve an increase in the breakdown voltage. In principle, it is known from the prior art, for example from U.S. Pat. No. 4,809,047 or U.S. Pat. No. 4,837,606, to carry out implantations of doping material in order to achieve a doping profile in the body region. However, these profiles are not suitable for achieving a reduction in the on resistivity and an improvement of the dielectric strength of the transistor arrangement in the manner according to the invention.
The dose of the first implantation can be chosen to be greater than the dose of the second implantation by a factor in the range from 10 to 1000. Specifically, in this case the first implantation can be chosen to be approximately a factor of 100 greater than the dose of the second implantation.
Should still further variation of the doping profile of the body region be desired, then it is possible to provide additional method steps in which doping material is introduced into the region of the body region. Thus, it may be provided that e.g. after doping material of the first conduction type has been deposited on the first surface, the doping material is diffused into the semiconductor body from the first surface in a diffusion step. What can thus be achieved is, for example, that the doping concentration can be set even more accurately in the region of the channel region, in order to set the threshold voltage of the transistor arrangement even more accurately to a desired value. Such a method step may be employed specifically when the transistor structure has a trench-type gate electrode.
It may also be provided that doping material of the first conduction type is introduced into the semiconductor body in an additional implantation step in such a way that the implantation maximum lies in the region of the channel region. The doping concentration in the channel region and thus the threshold voltage of the transistor arrangement can be influenced in a targeted manner by means of such a step. This method can be carried out in a relatively simple manner in particular when the gate electrode and thus the channel region lie in the region of the first surface of the semiconductor body. How
Gassel Helmut
Hirler Franz
Kanert Werner
Pairitsch Herbert
Strack Helmut
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