Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-26
2002-10-29
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S309000
Reexamination Certificate
active
06472262
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 0003845 filed Mar. 27, 2000, and is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor components, especially those intended to be integrated into high-frequency and Very Large Scale Integration (VLSI) technologies and more particularly, the present invention relater to fabricating self-aligned double-polysilicon type bipolar transistors with a silicon-germanium heterojunction base, especially those having an epitaxially grown base.
2. Description of Related Art
Generally, a double-polysilicon type bipolar transistor, has an extrinsic base and emitter are made of polycrystalline silicon (polysilicon). In contrast, a single-polycrystalline bipolar transistor only the emitter is made of polysilicon.
A double-polysilicon transistor is called “self-aligned” when the distance between the polysilicon of the extrinsic base and the polysilicon of the emitter is not defined by any photolithographic operation. Stated differently, a transistor is “self-aligned” regardless of any adjustment of two photolithographic masks, one mask with respect to the other mask.
In a conventional method for fabricating a self-aligned double-polysilicon bipolar transistor, the intrinsic base is implanted. A stack of layers comprising a polysilicon layer heavily doped with a conductivity type opposite to that of the substrate (for example p
+
-doped) is deposited over an active region of a semiconductor substrate having a given conductivity type (for example then n type). This polysilicon later is surmounted by an upper insulating layer, for example made of silicon dioxide. The p
+
polysilicon layer is intended eventually to form the extrinsic base of the transistor. The stack above the active region is then etched so as to define an emitter window. Electrically insulating regions or “spacers” are made on the walls of the emitter window. Next, polysilicon is deposited in the emitter window so as to form the emitter region. This emitter region is thus insulated from the extrinsic base by the internal spacers and also by a part of the upper insulating region of the stack on which this emitter region partially rests.
The above techinique for manufacturing self-aligned double-polysilicon transistors although useful is not without its shortcomings. One shortcoming is over-etching.
During the operation of etching the stack, over-etching occurs. The effect of over-etching is to remove part of the silicon from the active region. The control and the reproducibility of this over-etching for an implanted base transistor typically allows the intrinsic base to be implanted after opening the emitter window.
In contrast, the control and reproduciblity is much more difficult for a transistor with an epitaxially grown base. Moreover, this difficulty is especially true for an intrinsic base with a silicon-germanium heterojunction. Because, in the transistors with an epitaxially grown base, non-selective epitaxy is generally used to deposit a semiconducting region within which the future intrinsic base is made, over the active region and over the isolating regions delimiting this active region. The abovementioned stack of layers is then deposited on this first semiconducting region. However, the thickness of the first semiconducting region, that is to say the thickness of the intrinsic base, is particularly small, typically a few tens of nanometers. Also, this intrinsic base, which is already particularly thin to start with, is inevitably partially etched. Over-etching results from the etching of the stack which forms the emitter window. Over-etching leads to damage of the electrical operation of the transistor and may result in a defective transistor.
One solution of over-etching know in the art to overcome the above shortcomings, consists in epitaxially growing the intrinsic base after once the emitter window has been etched. However, such a solution requires the use of selective epitaxy, which presents other, more delicate, technological problems than for non-selective epitaxy. One problem is the requirement of tighter control of the thickness of the base. And another problem is ensuring ensuring the epitaxially grown base is of good quality.
Accordingly, a need exists to overcome the above problems and to provide a solution to overcome the over-etching during the formation of the stack in a self-aligned double-polysilicon transistor using non-selective epitaxy.
SUMMARY OF THE INVENTION
The present invention provides a method to make a transistor of the self-aligned double-polysilicon type with a heterojunction base, which uses non-selective epitaxy of the base while at the same time avoiding the problem of the overetching described above.
The present invention includes a method for fabricating a self-aligned double-polysilicon type bipolar transistor of with a heterojunction base, in which a semiconducting heterojunction region covering an active region of a semiconductor substrate and an isolating region surrounding the active region are formed by non-selective epitaxy. A stack comprising an etch-stop layer, for example made of silicon dioxide obtained from tetraethyl orthosilicate (TEOS), are formed on the semiconducting heterojunction region. This etch-stop layer is surmounted by a polysilicon layer having the same type of conductivity as the heterojunction region and overdoped with respect to this heterojunction region. Moreover, the stack comprises at least one upper insulating layer, for example, made of silicon oxide obtained from TEOS.
The stack is etched, stopping on the stop layer so as to define an emitter window above the active region. The portion of this stop layer situated at the bottom of the emitter window is removed and the stop layer is replaced locally by an electrically conducting replacement material at the outer periphery of the emitter window (for example, a heavily doped silicon-germanium alloy). The emitter region resting partially on the upper insulating layer of the stack is then formed in the emitter window.
Thus, the presence of the etch-stop layer makes it possible to prevent overetching of the semiconducting heterojunction region (which is intended to form the intrinsic base of the transistor) which has previously been obtained by non-selective epitaxy. In addition, the presence of the electrically conducting replacement material placed locally between the semiconducting heterojunction region and the polysilicon layer (which is intended to form the extrinsic base region of the transistor) makes it possible to ensure an electrical contact between the extrinsic base and the intrinsic base.
According to one method of implementing the invention, the heterojunction region comprises a layer made of a silicon-germanium alloy surmounted by a silicon layer. A replacement material, which is selectively removable with respect to the silicon, is then chosen. Also, after the emitter window is etched, the stop layer is removed from the bottom of the emitter window and locally under the polysilicon layer at the outer periphery of the emitter window. A layer formed from the replacement material is then deposited and then this layer formed from the replacement material is etched so as to leave the replacement material only between the heterojunction region and the polysilicon layer.
In one embodiment, two different materials are used for the stop layer and for the upper insulating layer of the stack. A stop layer made of silicon nitride could thus be used, while the upper insulating layer of the stack is made of silicon oxide obtained from TEOS. However, it is also possible for the stop layer to be formed from the same material as that forming the upper insulating layer of the stack, for example silicon oxide obtained from TEOS. In this case, a protective layer made of a material which is different to that of the stop layer (the protective layer could be
Baudry Hélène
Chantre Alain
Dutartre Didier
Fleit Kain Gibbons Gutman & Bongini P.L.
Gibbons Jon A.
Jorgenson Lisa K.
Nhu David
STMicroelectronics S.A.
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