Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-24
2001-10-16
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S234000, C438S324000, C438S365000
Reexamination Certificate
active
06303419
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to processes used to fabricate semiconductor devices, and more specifically to a process used to fabricate a bipolar—complimentary metal oxide semiconductor, (BiCMOS), device, on a semiconductor substrate.
(2) Description of Prior Art
The addition of bipolar junction transistors, to CMOS designs, results in a BiCMOS device, superior in performance to CMOS counterparts, as a result of the inclusion of the higher performing bipolar junction devices. An objective of the semiconductor industry has been to develop a process fabrication sequence, that allows integration of the bipolar, and CMOS devices, using shared process steps, and without sacrificing the performance of the bipolar junction transistor, as a result of having to use basically CMOS materials and processes.
This invention will describe a process for fabricating a BiCMOS device, in which a novel twin well, and epitaxial silicon layer, are featured, to arrive at a BiCMOS chip, formed using many shared, (bipolar and CMOS), process steps, and formed using an N type epitaxial layer, at a concentration, that allows the bipolar device, to achieve the desired performance requirements. Prior art, such as Ronkainen et al, in U.S. Pat. No. 5,776,807, describes a process for the fabricating a BiCMOS device, however this prior art does not describe the integration of the N type epitaxial layer, using a specific dopant level, needed to optimize bipolar performance, described in this present invention.
SUMMARY OF THE INVENTION
It is a principal object of this invention to design a BiCMOS structure which employs separate masks for the P well, as well as for the N well CMOS regions, while choosing the ideal N type epitaxial silicon layer for the NPN bipolar devices.
It is an object of this invention to integrate the fabrication of twin wells, a P well for the N type CMOS devices, and an N well for the P type CMOS devices, into the BiCMOS fabrication process.
It is another object of this invention to create a buried sub-collector region, for the bipolar device, while creating a buried N type layer, for the P type CMOS devices, using the same masking and ion implantation procedures.
It is still another object of this invention to integrate an N type, epitaxial layer, into the BiCMOS fabrication sequence, to be used as the collector region of the bipolar device.
It is still yet another object of this invention to use a split polysilicon layer, to protect the CMOS gate insulator layers from specific bipolar fabrication processes.
The design concept invention for BiCMOS is to form an N well region, for the P channel devices, and to form a P well region, for the N channel devices, and use an N type, epitaxial silicon layer for the NPN bipolar device. The N type epitaxial layer, in terms of dopant concentration, is specifically designed for the NPN bipolar devices. In prior BiCMOS designs the same N well, used for P channel devices, was used for the NPN bipolar device, particularly as CMOS fabrication is using a feature size of 0.25 uM, or less, and with an increased N well dopant concentration. The use of increased N well dopant concentration, for the NPN bipolar devices, is unsatisfactory, in terms of performance. In conventional BiCMOS designs the epitaxial layer, which could be either N type, or P type, is very low. However in this invention, using a feature size of 0.25 uM, or less, the epitaxial silicon layer must be N type, with the doping level designed to satisfy the NPN bipolar performance criteria. This will result in optimum CMOS, as well as NPN bipolar devices. In addition the process described in this present invention does not increase process steps or process complexity.
In accordance with the present invention a method of fabricating a BICMOS device, on a semiconductor substrate, featuring the use of an epitaxial silicon layer, for the bipolar device, and featuring the use of twin wells, for the CMOS devices, is described. After forming buried N type layers, in a first region of the semiconductor substrate, to be used for isolation of P type, (PFET), CMOS devices, and in a third region, to be used for the buried subcollector region, of the bipolar devices, a buried P type layer is formed in a second region of the semiconductor substrate, to be used for isolation of N type, (NFET), CMOS devices. An N type epitaxial silicon layer is grown, followed by the formation of an N well region, overlying the buried N type layer, in the first region, or in the PFET region, of the semiconductor substrate. After the creation of a heavily doped reach through region, contacting the buried subcollector layer, in the third region of the semiconductor substrate, a pattern in an oxidation resistant, composite layer, is formed on the regions of the semiconductor substrate, to be protected from a subsequent oxidation procedure, used to form isolation regions. After formation of a P well region, overlying the buried P type layer, in the second region, or in the NFET region of the semiconductor substrate, an oxidation procedure is performed, creating isolation regions, in areas not protected by the oxidation resistant, composite insulator layer, leaving subsequent active device regions, unoxidized.
Removal of the oxidation resistant, composite layer, is followed by the growth of a gate insulator layer, on the surface of all active device regions, followed by the deposition of a thin, first polysilicon layer. Conventional photolithographic and ion implantation procedures, are used to create a P type base region, in the collector region, located in the third region, or in the bipolar region, of the semiconductor substrate. Conventional photolithographic and dry etching procedures, are used to create an emitter opening in the thin, first polysilicon, followed by the formation of an N type, self-aligned collector region, ion implanted through the emitter opening, and located in the collector region, underlying the P type base region, and overlying the buried subcollector region. After removal of the gate insulator layer, exposed in the emitter opening, a thick, second polysilicon layer, is deposited, doped, and along with thin, first polysilicon layer, is patterned to create polysilicon gate structures, in the NFET and PFET regions, as well as creating a polysilicon emitter structure, contacting the base region, in the emitter opening. Conventional photolithographic block out masking, is used to allow a lightly doped, N type source/drain regions, to be formed in an area of the NFET region, not covered by the polysilicon gate structure, while similar photolithographic block out masking is used to allow a lightly doped, P type source/drain region to be formed in an area of the PFET region, not covered by a polysilicon gate structure. After formation of insulator spacers, on the sides of the polysilicon gate structures, and on the sides of the polysilicon emitter structure, an emitter drive-in cycle is performed, allowing dopant from the polysilicon emitter structure to diffuse into the top portion of the P type base region, creating an emitter region. Conventional photolithographic block out procedures, and conventional ion implantation procedures, are used to create the heavily doped N type, source/drain region, in an area of the NFET region, not covered by the polysilicon gate structure, or by the insulator spacers, followed by additional photolithographic block out masking, and ion implantation procedure, used to create the heavily doped, P type source/drain region, in an area of the PFET region, not covered by the polysilicon gate structure, or by insulator spacers.
REFERENCES:
patent: 5102811 (1992-04-01), Scott
patent: 5543653 (1996-08-01), Grubisich
patent: 5776807 (1998-07-01), Ronkainen et al.
patent: 5953600 (1999-09-01), Gris
patent: 6093613 (2000-07-01), Verma et al.
patent: 6100124 (2000-08-01), Iwamoto
patent: 6103560 (2000-08-01), Suzuki
patent: 6218253 (2001-04-01), Kishi
Chang Kuan-Lun
Tsui Bing-Yue
Ackerman Stephen B.
Industrial Technology Research Institute
Nguyen Tuan H.
Saile George O.
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