Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-16
2002-03-12
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S270000, C438S396000, C438S430000, C438S589000
Reexamination Certificate
active
06355520
ABSTRACT:
BACKGROUND
1. Technical Field
This disclosure relates to semiconductor memory fabrication and more particularly, a method for fabricating improved gate conductors.
2. Description of the Related Art
Semiconductor memory cells include capacitors accessed by transistors to store data. Data is stored by as a high or low bit depending on the state of the capacitor. The capacitor's charge or lack of charge indicates a high or low when accessed to read data, and the capacitor is charged or discharged to write data from the capacitor.
Stacked capacitors are among the types of capacitors used in semiconductor memories. Stacked capacitors are typically located on top of the transistor used to access a storage node of the capacitor as opposed to trench capacitors which are buried in the substrate of the device. As with many semiconductor devices, higher density in a smaller layout area is preferable. Memory cells for semiconductor devices may occupy an area of 4F
2
(where F is a minimum feature size of a technology) to provide reduced area and higher memory cell packing density.
For conventional 4F
2
stacked capacitor DRAMs, spacer type gate structures or wrap-around type gate structures (surrounded gate) are typically used to fit 4F
2
design rules. (See, e.g., M. Terauchi et al. “A surrounding gate transistor (SGT) gain cell for ultra high density DRAMS,” Symp. on VLSI Technology, pp. 21-22, 1993. These gate structures suffer from many disadvantages despite their area efficient structure. One disadvantage includes high resistance of the gate conductor due to the gate conductor's narrow geometry. This impacts the overall cell performance. Referring to
FIG. 1
, a layout for 4F
2
memory cells each having stacked capacitors with a space gate design is shown. In the layout, stacked capacitors
10
are disposed in rows and columns. Active areas
12
are disposed below stacked capacitors
10
. Active areas
12
are surrounded by shallow trench isolation regions
14
. A spacer gate
17
extends along active areas
12
. Spacer gates
17
are in pairs and have a dielectric material
13
(STI oxide) formed between them.
Referring to
FIG. 2
, a cross-section of the layout of
FIG. 1
is taken at section line
2
—
2
. Stacked capacitors
10
are shown having a top electrode
16
, a bottom electrode
18
and a capacitor dielectric layer
20
therebetween. Bottom electrode
18
is connected to a plug or capacitor contact
22
which extends down to a portion of active area
12
. Active areas
12
form an access transistor for charging and discharging stacked capacitor
10
in accordance with data on a buried bitline
24
. Bitline
24
is coupled to a portion of active area
12
(source or drain of the access transistor). When a gate conductor or spacer gate
17
is activated the access transistor conducts and charges or discharges stacked capacitor
10
. As illustrated, spacer gates
17
suffer from high resistance which is compounded if spacer gates are formed too thin or contain anomalies such as voids, etc.
Referring to
FIG. 3
, a layout is shown for 4F
2
memory cells having stacked capacitors and wrap around gates. In the layout, stacked capacitors
30
are disposed in rows and columns. Active areas
32
are disposed below stacked capacitors
30
, similar to FIG.
1
. Active areas
32
are surrounded by wrap around gates
31
. Shallow trench isolation regions (STI)
34
occupy regions adjacent to wrap around gates
31
.
Referring to
FIG. 4
, a cross-sectional view is shown taken at section line
4
—
4
of FIG.
3
. Stacked capacitors
30
are shown having a top electrode
36
, a bottom electrode
38
and a capacitor dielectric layer
40
therebetween. Bottom electrode
38
is connected to a plug
42
which extends down to a portion of active area
32
. Active areas (AA)
32
form an access transistor for charging and discharging stacked capacitor
30
in accordance with data on a buried bitline
44
. Bitline
44
is coupled to a portion of active area
32
(source or drain of the access transistor). When wrap around gate
31
is activated the access transistor conducts and charges or discharges stacked capacitor
30
. As illustrated, wrap around gates
31
also suffer from high resistance which is compounded if wrap around gates are formed too thin or contain anomalies such as voids, etc.
In both cases described above, the geometry of gate conductors is highly limited by design rules. Since the cross-sectional area of gate conductor is quite narrow, the resistance of gate conductors is fairly high and can adversely affect the overall cell performance. The use of highly conducting materials such as silicides or metals are also limited by the small geometry of the gate conductor.
Therefore, a need exists for an improved layout for stacked capacitor memory cells with 4F
2
area which provides lower gate resistance and improved cell performance. A further need exists for a method for fabricating gates for the stacked capacitor memory cells.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for forming gate conductors in 4F
2
area stacked capacitor memory cells includes the steps of forming a buried bit line in a substrate, forming an active area above and in contact with the buried bit line and separating portions of the active area by forming a dielectric material in trenches around the portions of the active area. Portions of the dielectric material are removed adjacent to and selective to the portions of the active area. A first portion of a gate conductor is formed in locations from which the portion of dielectric material is removed, and a second portion of the gate conductor is formed on a top surface of the dielectric material and in contact with the first portion of the gate conductor. Stacked capacitors are formed such that the gate conductor activates an access transistor formed in the portions of the active area.
Another method, in accordance with the present invention, for forming gate conductors in 4F
2
area stacked capacitor memory cells includes the steps of forming a buried bit line in a substrate, forming an active area above and in contact with the buried bit line and separating portions of the active area by forming a dielectric material in trenches around the portions of the active area. Then by removing portions of the dielectric material adjacent to and selective to the portions of the active area, a gate oxide is formed on portions of the active area exposed by the removal of portions of the dielectric material. The method also includes the steps of forming a first portion of a gate conductor in locations from which the portion of dielectric material is removed. The first portion of the gate conductor is in contact with a single portion of the portions of the active area. A second portion of the gate conductor is formed on a top surface of the dielectric material and in contact with the first portion of the gate conductor wherein the second portion of the gate conductor includes a height which is adjusted to provide a desired gate resistance. A pad stack is created by forming a conductive material on the second portion of the gate conductor and forming stack capacitors such that the gate conductor activates an access transistor formed in the single portion of the active area.
In alternate methods, the first portion of the gate conductor preferably extends adjacent to the active area a vertical distance of greater than or equal to about 1F where F is a minimum feature size for a given technology. The vertical distance preferably represents a transistor channel length for the access transistor. The step of spacing adjacent gate conductors a horizontal distance of at least 1F apart where F is a minimum feature size for a given technology may be included. The method may further include the step of adjusting a height of the second portion to adjust gate conductor resistance.
The method may further include the step of forming one of a metal and a polycide on the second portion of the gate conductor to form a gate stack. The method may inc
Lee Heon
Park Young-jin
Infineon - Technologies AG
Thomas Toniae M.
Wilczewski Mary
LandOfFree
Method for fabricating 4F2 memory cells with improved gate... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for fabricating 4F2 memory cells with improved gate..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for fabricating 4F2 memory cells with improved gate... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2887341