Method for extending lifetime reliability of digital logic...

Details Method for extending lifetime reliability of digital logic... Method for extending lifetime reliability of digital logic...

2008-05-20

2009-02-03

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Signal level or switching threshold stabilization

C326S034000, C326S095000, C326S098000, C327S537000, C327S534000

Reexamination Certificate

active

07486107

ABSTRACT:
A method for extending lifetime reliability of CMOS circuitry includes configuring a logic high supply rail, a logic low supply rail, and a virtual supply rail. In an intense recovery mode of operation, a first switching device is rendered nonconductive to isolate the virtual supply rail from the one of the logic high supply rail and the logic low supply rail, and the second switching device is rendered conductive so as to equalize the voltage on the virtual supply rail and the other of the logic high supply rail and the logic low supply rail. At least one device within the circuitry provides one of the logic high voltage and the logic low voltage to a gate terminal of an FET within the circuitry, with a source terminal of the FET coupled to the virtual supply rail, such that the FET is subjected to a reverse bias condition.

REFERENCES:
patent: 6329874 (2001-12-01), Ye et al.
patent: 6559708 (2003-05-01), Notani
patent: 7145383 (2006-12-01), Mizuno et al.
patent: 7190209 (2007-03-01), Kang et al.

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