Method for evaluating property of integrated circuitry

Semiconductor device manufacturing: process – With measuring or testing

Reexamination Certificate

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Details

C438S015000, C438S017000, C438S131000

Reexamination Certificate

active

06869808

ABSTRACT:
There are provided a method for evaluating, in a reduced number of steps, a property of an integrated circuit reflecting operating conditions for an actual LSI and the design of the LSI. The property (delay) of a circuit A (ring oscillator) in a wafer or mounted chip is measured actually or simulated and the property of a circuit B (LSI) is simulated. Then, the interrelation between the degree of property degradation of the circuit A and the degree of property degradation of the circuit B is determined. The circuit property of a circuit AA (ring oscillator) having substantially the same degree of property degradation as the circuit A and manufactured under a new manufacturing condition is measured actually or simulated so that the degree of property degradation of a circuit BB is predicted from the interrelation and the degree of property degradation of the circuit AA. The circuit BB has substantially the same degree of property degradation as the circuit B and is manufactured under a new manufacturing condition.

REFERENCES:
patent: 5650336 (1997-07-01), Eriguchi et al.
patent: 6389381 (2002-05-01), Isoda et al.
patent: 6560716 (2003-05-01), Gasparik et al.
patent: 63-177437 (1988-07-01), None
patent: 4-160377 (1992-06-01), None
patent: 8-139279 (1996-05-01), None
patent: 11-118874 (1999-04-01), None
patent: 11-166960 (1999-06-01), None

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